1. No category

DOMINIK MEYER
byterazor@federationhq.de
30C3
Overview
1 Introduction
2 Requirements
3 Functional Principle
4 Processor Simulation
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Processor Design
1/24
FPGA Board
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Processor Design
Requirements
2/24
HDL Knowledge
for example VHDL
e n t i t y c3b4bencoding i s
port (
iRD
: in s t d _ l o g i c ;
iK
: in s t d _ l o g i c ;
iWord : i n s t d _ l o g i c _ v e c t o r ( 2 downto 0 ) ;
oWord : out s t d _ l o g i c _ v e c t o r ( 3 downto 0 )
);
end c3b4bencoding ;
english http://tams-www.informatik.uni-hamburg.
de/vhdl/doc/cookbook/VHDL-Cookbook.pdf
german http://tams-www.informatik.uni-hamburg.
de/vhdl/doc/ajmMaterial/vhdl.pdf
byterazor
Processor Design
Requirements
3/24
Not working alone !
System on Chip (SOC)
Addressbus
RAM
Processor Core
Databus
Registerfile
Serial Device
memory mapped IO
Remember: memory access is very slow, compared to intra
processor memory
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Processor Design
Functional Principle
4/24
Instruction Set Architecture
byterazor
Mnemonic
Parameter
Description
li
loa
sto
shl
shr
add
sub
addc
subc
or
and
xor
not
jpz
jpc
jmp
dst,<immidiate>
dst,<address>
op1,<address>
dst,op1
dst,op1
dst,op1,op2
dst,op1,op2
dst,op1,op2
dst,op1,op2
dst,op1,op2
dst,op1,op2
dst,op1,op2
dst,op1
<address>
<address>
<address>
dst = immediate
dst = RAM (address)
RAM (address) = op1
dst = shl(op1)
dst = shr(op1)
dst = op1 + op2
dst = op1 − op2
dst = op1 + op2 + C
dst = op1 − op2 − C
dst = op1orop2
dst = op1andop2
dst = op1xorop2
dst = notop1
jump if zero to <address>
jump if carry to <address>
jump to address
Processor Design
Functional Principle
5/24
Small C Programm
/ / very simple m u l t i p l i c a t i o n
i n t main ( ) {
i n t a =5;
i n t b =6;
i n t r e s u l t =0;
int i ;
f o r ( i =0; i <b ; i ++) {
r e s u l t += a ;
}
return 0;
}
byterazor
Processor Design
Functional Principle
6/24
Assembler Code
main:
li $1, 5
li $2, 6
li $3, 0
li $4, 1
add $5, $0, $2 #because we have no move instr
loop:
add $3,$3,$1
sub $5,$5,$4
jpz end
jmp loop
end:
byterazor
Processor Design
Functional Principle
7/24
Instruction Encoding
31
20
25
Opcode
15
Operand1
Result
9
0
Operand2
Immediate/Address
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Processor Design
Instruction
Opcode
li
add
sub
jpz
jmp
hlt
001111
000100
000101
001100
001110
111111
Functional Principle
8/24
Assembling + RAM Image
Address
0
1
2
3
4
5
6
7
8
9
byterazor
Data
Comment
001111_00001_00000_00000_00000000101
001111_00010_00000_00000_00000000110
001111_00011_00000_00000_00000000000
001111_00100_00000_00000_00000000001
000100_00101_00000_00010_00000000000
000100_00011_00011_00001_00000000000
000101_00101_00101_00100_00000000000
001100_00000_00000_00000_00000001001
001110_00000_00000_00000_00000000101
111111_00000_00000_00000_00000000000
li $1, 5
li $2, 6
li $3, 0
li $4, 1
add $5, $0, $2
add $3, $3, $1
sub $5, $5, $4
jpz end
jmp loop
hlt
Processor Design
Functional Principle
9/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 0
1
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
0
0
RegisterBsel
0
0
3
0
Result 0
JMP
0
0
RegisterRessel
1
ADDR
0
2
0
4
0
Carry 0
0
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
1
0
0
0
shl
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
1
0
OpCode
0
LoadInstr AddrSel
1
1
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Load
Zero
Carry
LoadEn 0
Processor Simulation
10/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 0
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
1
0
RegisterBsel
0
0
3
0
Result 5
JMP
0
1
RegisterRessel
1
ADDR
0
2
0
4
0
Carry 0
0
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
1
0
1
5
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
5
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Decode
Zero
Carry
LoadEn 0
Processor Simulation
11/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 0
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 1
RegisterFile
PC
1
0
RegisterBsel
0
0
3
0
Result 5
JMP
0
1
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
0
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
0
0
5
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
5
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Execute li
Zero
Carry
LoadEn 1
Processor Simulation
12/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 1
1
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
1
0
RegisterBsel
0
0
3
0
Result 5
JMP
0
1
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
0
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
1
0
5
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
5
LoadInstr AddrSel
1
1
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Load
Zero
Carry
LoadEn 0
Processor Simulation
13/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 1
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
2
0
RegisterBsel
0
0
3
0
Result 6
JMP
0
2
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
0
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
1
0
1
6
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
6
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Decode
Zero
Carry
LoadEn 0
Processor Simulation
14/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 1
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 1
RegisterFile
PC
2
0
RegisterBsel
0
0
3
0
Result 6
JMP
0
2
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
6
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
0
0
6
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
6
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Execute li
Zero
Carry
LoadEn 1
Processor Simulation
15/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 2
1
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
2
0
RegisterBsel
0
0
3
0
Result 6
JMP
0
2
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
6
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
1
0
6
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
6
LoadInstr AddrSel
1
1
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Load
Zero
Carry
LoadEn 0
Processor Simulation
16/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 2
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
3
0
RegisterBsel
0
0
3
0
Result 0
JMP
0
3
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
6
5
0
Zero
1
1
AddrSel
incPC
Jump
LoadInstr
1
0
1
0
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
0
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Decode
Zero
Carry
LoadEn 0
Processor Simulation
17/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 2
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 1
RegisterFile
PC
3
0
RegisterBsel
0
0
3
0
Result 0
JMP
0
3
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
6
5
0
Zero
1
1
AddrSel
incPC
Jump
LoadInstr
0
0
0
0
0
li
0
0
1
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
0
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Execute li
Zero
Carry
LoadEn 1
Processor Simulation
18/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 3
1
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
3
0
RegisterBsel
0
0
3
0
Result 0
JMP
0
3
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
6
5
0
Zero
1
1
AddrSel
incPC
Jump
LoadInstr
0
1
0
0
0
li
0
0
1
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
0
LoadInstr AddrSel
1
1
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Load
Zero
Carry
LoadEn 0
Processor Simulation
19/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 3
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
4
0
RegisterBsel
0
0
3
0
Result 1
JMP
0
4
RegisterRessel
1
ADDR
0
2
5
4
0
Carry 0
6
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
1
0
1
0
li
0
0
1
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
1
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Decode
Zero
Carry
LoadEn 0
Processor Simulation
20/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 3
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 1
RegisterFile
PC
4
0
RegisterBsel
0
0
3
0
Result 1
JMP
0
4
RegisterRessel
1
ADDR
0
2
5
4
1
Carry 0
6
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
0
0
1
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
1
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Execute li
Zero
Carry
LoadEn 1
Processor Simulation
21/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 4
1
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
4
0
RegisterBsel
0
0
3
0
Result 1
JMP
0
4
RegisterRessel
1
ADDR
0
2
5
4
1
Carry 0
6
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
1
0
1
0
li
0
0
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
1
LoadInstr AddrSel
1
1
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Load
Zero
Carry
LoadEn 0
Processor Simulation
22/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 4
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 0
RegisterFile
PC
5
2
RegisterBsel
0
0
3
0
Result 6
JMP
0
5
RegisterRessel
1
ADDR
0
2
5
4
1
Carry 0
6
5
0
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
1
0
1
0
0
add
0
6
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
6
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Decode
Zero
Carry
LoadEn 0
Processor Simulation
23/24
Simulation
RAM
0
001111 00001 00000 00000 00000000101
5
000100 00011 00011 00001 00000000000
1
001111 00010 00000 00000 00000000110
6
000101 00101 00101 00100 00000000000
2
001111 00011 00000 00000 00000000000
7
001100 00000 00000 00000 00000001001
3
001111 00100 00000 00000 00000000001
8
001110 00000 00000 00000 00000000101
4
000100 00101 00000 00010 00000000000
9
111111 00000 00000 00000 00000000000
RnW addr data
MEM_IF
Address 4
0
0
RegisterAsel
Fetch/Decode
Instruction
LoadEn 1
RegisterFile
PC
5
2
RegisterBsel
0
0
3
0
Result 6
JMP
0
5
RegisterRessel
1
ADDR
0
2
5
4
1
Carry 0
6
5
6
Zero
0
1
AddrSel
incPC
Jump
LoadInstr
0
0
0
0
0
add
0
6
0
0
OP1
OP2
Zero
Carry
ALU
Immidiate
0
0
OpCode
6
LoadInstr AddrSel
1
0
byterazor
incPC
RnW
Enable
Processor Design
Jump OpCode
Control Unit
State
Execute add
Zero
Carry
LoadEn 1
Processor Simulation
24/24