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Assignment for Lab 9
Cache and Datapath
Computer Science 240
In lab 9, you will experiement with cache memory and with a datapath implementation
for a small instruction set architecture.
1.
For each of the following independent assignments of bits in a 32-bit address for
use in a direct-mapped cache, answer the following questions.
Tag
A 31-10
B 31-12
a.
Index Offset
9-4
3-0
11-5
4-0
What is the cache line size in bytes?
b.
How many entries does the cache have? (In other words, how many data
lines/blocks can the cache store in total?)
c.
What is the ratio between the total bits used by the cache over the bits required to
store the data entries alone?
2.
Starting from an empty cache, the following byte addresses are accessed in order
(decimal notation is used): 0 4 16 132 232 160 1024 30 140 3100 180 2180
a.
Show the final state of each valid entry in the cache by listing pairs of (index, tag)
for each index in the cache.
b.
How many lines/blocks are replaced?
c.
What is the hit rate?
3. You will be spending part of the lab today implementing and experimenting with the
datapath for a simple instruction set architecture. After reading the specification for the
architecture described below, answer these questions:
a. How many instructions are there in the instruction set?
b. How many bits are there in each instruction?
c. What instruction is represented by the hexadecimal value 0x0123? What does it do?
d. What is the 16-bit binary form of the following instruction (pay attention to the order
of operands):
ADD R1 R1 R4
What are the contents of Register 1 and Register 4 after this instruction is executed?
e. Given the following instruction at address 8 in memory:
8: BEQ R5 R6 C
Assume register 5 contains FFFE, and register 6 contains FFFE.
After this instruction is executed, what will be the address of the next instruction?
f. Repeat question e, but assume that the original value of register 5 = 0003, and register
6 = 0002. What will be the address of the next instruction?
Description of Instruction Set Architecture
The datapath you will investigate in lab is for a simple RISC-style CPU, which is
simpler than X86. In a RISC architecture, a small number of highly efficient instructions
and addressing modes are used (this makes it fairly straightforward to design a hardware
implementation for the ISA).
The word length for this device is 16 bits.
The starting address of every program will be address 0, which is set when the program
counter is initialized to 0 by a reset.
Because instructions are 16 bits in length, the program counter must be incremented by 2
to move to the next instruction.
There are 16 registers available, 14 general-purpose registers (R2-R15) and 2 constant
value registers (R0-R1). The R0 register always contains 0 and the R1 register always
contains 1. Neither R0 nor R1 can be modified by any instruction.
Instructions specify register IDs using 4-bit values. The program counter is an 8-bit
register, but it cannot be directly accessed by any instruction.
The following instruction set is defined (all instructions are one word in length):
Instruction
LW Rt,offset(Rs)
SW Rt,offset(Rs)
ADD Rs,Rt,Rd
SUB Rs,Rt,Rd
AND Rs,Rt,Rd
OR Rs,Rt,Rd
SLT Rs,Rt,Rd
BEQ Rs,Rt,offset
JMP offset
Meaning
Opcode Rs
4-bit 4-bit
Rt gets word
0000 0-15
read from memory at
address (Rs + offset)
Rt
4-bit
0-15
Rd/offset
4-bit
offset
Contents of Rt is
0001
written to memory at
Address (Rs + offset)
Rd := Rs + Rt
0010
Rd := Rs - Rt
0011
Rd := Rs AND Rt
0100
Rd := Rs OR Rt
0101
If Rs<Rt then
0110
Rd:=1
else
Rd := 0
If Rs=Rt then
0111
pc:=pc+2+(offset*2)
else
pc:=pc+2
Jump to
1000
address = offset*2
0-15
0-15
offset
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
0-15
offset
---12 bit offset-----
The most significant four bits of each instruction (opcode) specify the operation. Rs and
Rt are usually source registers, and Rd is the destination register.
There are 3 instruction formats:
• Math/logic operations (ADD, SUB, AND, OR, SLT) operate only on registers.
• Memory access and branching operations (LW, SW, BEQ) operate on two
registers and an absolute offset value.
• The jump operation (JMP) operates on a single 12-bit offset.
Data in memory can only be accessed using the LW (load word) or SW (store word)
instructions. For these, Rs contains the base address of the location in memory that is
being accessed, and the offset is added to the base address to determine the location in
memory that is being read from (load word) or written to (store word).
Addition, subtraction and set-greater-than treat the contents of Rs and Rt as 16 bit, two’s
complement numbers. Logical operations (AND,OR) treat Rs, Rt and Rd as unsigned, 16
bit values.
Load and store operations use the low 12 bits to specify memory address,
source/destination register and offset respectively. Rs specifies the register containing a
base address. Rd specifies the offset and Rt specifies the destination (or source) for data
being read (or stored). Note that the only addressing mode is register indirect.
The branch equal (BEQ) operator uses the low 12 bits to specify the registers for
comparison and the branch offset. Rs and Rt specify registers whose values are to be
compared. If they are equal, the program counter is incremented by (2 * offset).
Offsets for loading, storing and branching are 4 bit, 2’s complement numbers that specify
offsets as words. Be cautious as you add and subtract offsets to get new program counter
values. The length of the offset limits how far a program can branch using the BEQ
command.
The jump operation uses the low 12 bits to specify a single offset value (this value should
be in the range of 0 to 127, to guarantee a legal address within the range of 0 to 255. The
jump offset is interpreted a positive value, and the JMP operation is achieved by setting
the program counter to the offset * 2.