杨涛) Alan Yang( 现场应用工程师) Field Applications Engineer (

TM
Alan Yang(杨涛)
Field Applications Engineer (现场应用工程师)
August 2012
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
TM
names are the property of their respective owners. © 2012 Freescale Semiconductor,
Inc.
.
1
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
MPC560xB Overview(概述)
•
Clock Generation Module(时钟模块)
•
Run Modes(运行模式)
•
Low Power & Power Management Unit(低功耗和低功耗单
元)
•
RTC/API
•
Wakeup(单片机唤醒)
•
Hands-on session(实例)
TM
2
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Up to 32k cache
Dual Issue /VLE
e200z7
7-stage pipeline
Performance / Features
性
能/
特
性
10-stage pipeline
7-stage pipeline
Up to 32k cache
5-stage pipeline
VLE
Up to 16k cache
e200z6
Dual Issue / VLE
200 MHz
Up to 32k cache
FPU
SIMD
120 MHz
FPU
144 MHz
SIMD
FPU
e200z4
SIMD
e200z6
FPU
266 MHz
SIMD
4-stage pipeline
VLE
e200z3
4-stage pipeline
80 MHz
VLE
FPU
SIMD
e200z1
4-stage pipeline
64 MHz
VLE Only
e200z0
64 MHz
2005
2004
TM
2006
3
2007
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Entry BCM
Mid-High BCM
Integrated
Gateways
MPC5668G
Production产品
Security
z6+z0, 116MHz,
Up to 2M Flash, 598k RAM
FlexRay, Ethernet, MLB,
CANx6, LINx6
MPC5646/5/4C
MPC5668E
MPC5646/5/4B
z6+z0, 116MHz,
Up to 2M Flash, 128k RAM
CANx5, LINx12
z4, 120MHz,
Up to 3M Flash, 192k RAM,
FlexRay, CANx6, LINx10,
Security
MPC5607/6/5/B
Dual Core双核
z4+z0, 120MHz,
Up to 3M Flash, 256k RAM,
FlexRay, Ethernet, CANx6,
LINx10, Security
Single Core单核
Security
z0, 64MHz,
Up to 1.5M Flash, 96k RAM
CANx6, LINx10
MPC5604/3/2/B/C
z0, 64MHz,
Up to 512k Flash, 48k RAM
CANx6, LINx4
MPC5602/1D
z0, 48MHz,
Up to 256k Flash, 16k RAM
CANx1, LINx3
Past
TM
2012
4
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
System
Integration
“Monaco”
“Pictus”
“Bolero”
“Spectrum”
(Powertrain)
(Steering/Airbag)
(Body/Gateway)
(Inst Cluster)
Crossbar Masters
Debug
Crossbar Masters
PowerPC TM
e200z3
Core
SIMD
MMU
JTAG
System
Integration
DMA
RTC
Nexus
FMPLL
DMA
I/O
Bridge
Boot
Assist
Module
(BAM)
Nexus
Oscillator
PowerPC TM
e200z0
Core
FMPLL
DMA
RTC
PIT 4ch 32b
Nexus
Display
Interface
Unit
Interrupt
Controller
Mc Timer
32 ch
ATD
12bit
512Kb
Flash
CROSSBAR SWITCH
CROSSBAR SWITCH
Memory Protection Unit (MPU)
Memory Protection Unit (MPU)
32K
SRAM
I/O
Bridge
Power Sw
Boot
Assist
Module
(BAM)
Crossbar Slaves
Communications I/O System
2
DSPI
DMA
Ready
RTC
40K
SRAM
512Kb
Flash
Mc Timer
2
eSCI
PowerPC TM
e200z0
Core
FMPLL
Crossbar Slaves
Mc Timer
2
FlexCAN
JTAG
1Mb
Flash
Video
RAM
(tbd )
64K
SRAM
External
Bus
(208MAPBGA)
Boot
Assist
Module
(BAM)
Crossbar Slaves
Communications I/O System
Communications I/O System
ADC I/F
10 bit
650 nsec
S&H S&H
mux mux
1or2
FlexCAN
1
eSCI
3
DSPI
eMIOSLite
8ch IO
36ch shift
PWM
2
I2 C
3
FlexCAN
4
LINFlex
3
DSPI
32 ch
ATD
12bit
eMIOSLite
24 ch.
2
CAN
2
LIN
Flex
3
DSPI
2
I2 C
16 ch
ATD
10bit
6
gauge
drivers
sound
eTPU
32 ch.
Oscillator
Interrupt
Controller
Communications I/O System
2.5K Code
RAM
12K Data
RAM
Debug
VReg
CROSSBAR SWITCH
Boot
Assist
Module
(BAM)
Crossbar Slaves
Crossbar Masters
JTAG
MCM
I/O
Bridge
48K
SRAM
Nexus
FlexRay
Interrupt
Controller
Cal Bus Interface
CROSSBAR SWITCH
1Mb
Flash
PowerPC TM
e200z0
Core
RTC
Interrupt
Controller
Debug System
Integration
Crossbar Masters
VReg
Oscillator
Mc PWM
FMPLL
eMIOSLite
24ch
Debug
VReg
Oscillator
I/O
Bridge
System
Integration
JTAG
VReg
32-bit standard architecture adopted across all product families
32位标准架构,适用于所有产品系列
•
•
•
•
Maximum IP reuse(最多的模块复用)
Optimized design and test flow(优化的设计测试流程)
Consolidated tool chain(统一的工具链)
Strong marketing message in compatibility(最好的兼容性)
TM
5
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
40x4
LCD
•
System
Integration
Crossbar
Masters
PIT 4ch 32b
−
−
−
−
Debug
JTAG
VReg
CORE
•
MEMORY
−
PowerPCTM
Power Mgt
Nexus 2+
e200z0
Core
Oscillator
FMPLL
−
−
−
−
Interrupt
Controller
•
CROSSBAR SWITCH
−
3x enhanced FlexCAN
−
−
−
4x LINFlex
3x DSPI, 8-16 bits wide & chip selects
1x I²C

Standby RAM
512K
Flash
•
48K SRAM
64K Data
Flash
Boot
Assist
Module
(BAM)
Crossbar Slaves
−
3
FlexCAN
4
LINFlex
3
DSPI
1
I2C
TIMED I/O
•
OTHER
−
−
−
TM
6
5V ADC 10-bit resolution
•
−
−
CTU 36 ch
ADC
10bit
64 Message Buffers each, full CAN 2.0 spec
ANALOG
−
Communications I/O System
eMIOSLite
6ch IC/OC
50ch PWM
512Kbyte embedded program flash, 64 KByte
data flash
64 Kbyte embedded data Flash (for EE
emulation)
Up to 64 MHz non-sequential access with 2WS
ECC-enabled array with error detect/correct
48 Kbyte SRAM (single cycle access, ECCenabled)
COMMUNICATIONS
Memory Protection Unit (MPU)
I/O
Bridge
PowerPC e200z0 core running 48-64 MHz
VLE ISA instruction set for superior code density
Vectored interrupt controller
Memory Protection Unit with 8 regions, 32 byte
granularity
16-bit eMIOS module
CTU (Cross Triggering Unit) to sync ADC with
PWM Channels
Debug: Nexus 2+
I/O: 5V I/O, high flexibility with selecting GPIO
functionality
Packages: 100LQFP, 144LQFP, 208MAPBGA
(Development only)
Boot Assist Module for production and bench
programming
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Additional DMA, bigger memories,
Additional 12-bit ADC, richer peripheral set
System
Integration
Crossbar
Masters
Debug
VReg
PIT 4ch 32b
•
CORE
−
JTAG
−
PowerPCTM
e200z0
Core
Power Mgt
Oscillator
FMPLL
Nexus 2+
DMA
Interrupt
Controller
−
−
•
PowerPC e200z0 core running at 64 MHz @
Ta=105C (48 Mhz at 85oC Base)
VLE ISA instruction set for superior code
density
Vectored interrupt controller
Memory Protection Unit with 16 regions, 32 byte
granularity
MEMORY
−
−
−
−
−
CROSSBAR SWITCH
Memory Protection Unit (MPU)
•
I/O
Bridge
1.5M
Flash
64K Data
Flash
6
FlexCAN
96K SRAM
Crossbar Slaves
10
LINFlex
6
DSPI
COMMUNICATIONS
−
6x enhanced FlexCAN
−
−
−
10 x LINFlex
6 x DSPI, 8-16 bits wide and chip selects
1 x I²C
•
Standby RAM
Boot
Assist
Module
(BAM)
Communications I/O System
eMIOS
64ch, 16 bit
1
I2C
•
−
TIMED I/O
•
OTHER
−
−
−
−
7
Up to 52 ch. 5V ADC (16x12-bit, 36x10-bit)
resolution
•
−
Up to 52 ch
ADC
16x12bit,
36x10 Bit
64 message buffers each, full CAN 2.0 spec
ANALOG
−
TM
1.5 Mbyte embedded program flash
64 Kbyte embedded data Flash (for EE
emulation)
Up to 64 MHz non-sequential access with 2WS
ECC-enabled array with error detect/correct
96Kbyte SRAM (single cycle access, ECCenabled)
16-bit eMIOS module, 64-ch.
32 channel DMA controller
Debug: Nexus 2+
I/O: 5V I/O, high flexibility with selecting GPIO
functionality
Packages: 100LQFP, 144LQFP, 176LQFP,
208MAPBGA (TBD)
Boot Assist Module for production and bench
programming
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
The crossbar increases overall
system performance by providing up
to two simultaneous connections
between
− 3 master ports
Example Access:
•
•
z0 instruction fetch from flash
eDMA SRAM access
e200z0 uses 2 master ports
−
•
•
CPU
e200z0
3 slave ports
32-bit address and 32-bit data on
Bolero
Data
eDMA
Controller
Instr:
Crossbar
The eDMA offloads the processor
tasks for data movement
Flash controller
SRAM
•
Timers can initiate complex DMA
sequences (channel link) to have
automatic peripheral management
without CPU load
TM
IP Bus i/f to
peripherals
and I/Os
FLASH
Crossbar 3Mx3S
8
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Summary
Real Time Operating Systems,
Virtualization and Middleware
Trace-powered multi-core
debugging that FINDS
EVERY BUG
Qorivva
MPC55xx, 56xx, 57xx
Powertrain, body, safety
ADAS, chassis
Nexus JTAG and Trace
Probes
TM
Professional development
tools and world’s fastest
Qorivva compilers
Support & Services
9
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
TM
names are the property of their respective owners. © 2012 Freescale Semiconductor,
Inc.
.
•
Overview of Platform Clocks时钟模块总览
•
FIRC (16 MHz), FXOSC (4 – 16 MHz),
SIRC (128 KH z), SXOSC (32 KHz)
•
FMPLL
•
CMU
10
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
MPC560xB CGM clock sources
• Main clock sources(主时钟源)
− 4-16
MHz external crystal/oscillator -> FXOSC (Fast eXternal Osc)
− 16 MHz internal RC oscillator -> FIRC (Fast Internal RC)

Default system clock after reset
 Trimmable
•
Low power clock sources(低功耗时钟源)
− 32
KHz external crystal/oscillator -> SXOSC (Slow eXternal Osc)

Low power oscillator
 Dedicated for RTC/API
•
128 KHz internal RC oscillator -> SIRC (Slow Internal RC)

Dedicated for RTC/API and watchdog
 Trimmable
TM
11
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FXOSC
4-16MHz
FIRC
16MHz
div 1 to 32
FXOSC_DIV
FIRC_DIV
div 1 to 32
SYSCLK
System
Clock
Selector
(ME)
FMPLL
FIRC
FXOSC
32KHz
128KHz
CMU
SXOSC
SIRC
SXOSC
32KHz
div 1 to 32
SIRC
128KHz
div 1 to 32
div 1 to 16
Peripheral Set 1
div 1 to 16
Peripheral Set 2
div 1 to 16
Peripheral Set 3
FIRC_DIV
SXOSC_DIV
API / RTC
SIRC_DIV
FXOSC
FIRC
FMPLL
TM
RESET
SAFE
INT
Core
Platform
SWT
(Watchdog)
CLKOUT
Selector
12
div 1/2/4/8
CLOCK OUT
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Provides the clock (divided or not) to the core/peripherals
• 提供时钟(分频或者不分频)给内核或者外设
• Selected by ME_XXX_MC register
• 通过ME_XXX_MC寄存器进行选择
SYSCLK
FXOSC
Core
Platform
FXOSC_DIV
FIRC
FIRC_DIV
FMPLL
TM
System
Clock
Selector
(ME)
Enable &
div 1 to 16
Peripheral Set 1
Enable &
div 1 to 16
Peripheral Set 2
Enable &
div 1 to 16
Peripheral Set 3
13
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Peripheral Set 1
Peripheral Set 2
Peripheral Set 3
All LINFlex modules
All FlexCAN modules
All eMIOS modules
I2C module
All DSPI modules
CTUL
ADC
DEx:
DIVx:
TM
Peripheral Set x Divider Enable (Default value 1 = ON)
Peripheral Set x Divider x Division Value (1..15)
14
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FXOSC
4-16MHz
FIRC
16MHz
div 1 to 32
FXOSC_DIV
FIRC_DIV
div 1 to 32
SYSCLK
System
Clock
Selector
(ME)
FMPLL
FIRC
FXOSC
32KHz
128KHz
CMU
SXOSC
SIRC
SXOSC
32KHz
div 1 to 32
SIRC
128KHz
div 1 to 32
div 1 to 16
Peripheral Set 1
div 1 to 16
Peripheral Set 2
div 1 to 16
Peripheral Set 3
FIRC_DIV
SXOSC_DIV
API / RTC
SIRC_DIV
FXOSC
FIRC
FMPLL
TM
RESET
SAFE
INT
Core
Platform
SWT
(Watchdog)
CLKOUT
Selector
15
div 1/2/4/8
CLOCK OUT
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Default clock after reset(重启后的默认时钟)
•
Division factors ranging from 1, 2, 3....32
•
Trimming (+/- 1%)
TM
16
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Bit
Name
Description
10-15
RCTRIM
RC trimming bits
19-23
RCDIV
RC division factor
17
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FXOSC
4-16 MHz
FIRC
16 MHz
div 1 to 32
FXOSC_DIV
FIRC_DIV
div 1 to 32
SYSCLK
System
Clock
Selector
(ME)
FMPLL
FIRC
FXOSC
CMU
32 KHz SXOSC
SIRC
128 KHz
SXOSC
32KHz
div 1 to 32
SIRC
128KHz
div 1 to 32
div 1 to 16
Peripheral Set 1
div 1 to 16
Peripheral Set 2
div 1 to 16
Peripheral Set 3
FIRC_DIV
SXOSC_DIV
API / RTC
SIRC_DIV
FXOSC
FIRC
FMPLL
TM
RESET
SAFE
INT
Core
Platform
SWT
(Watchdog)
CLKOUT
Selector
18
div 1/2/4/8
CLOCK OUT
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Division factors ranging from 1, 2, 3....32(分频系数范围)
•
Bypass mode to enable external clock source(旁路模式使
能外部时钟)
•
Clock ready interrupt flag (时钟准备完成中断标识)
− Configurable
start-up time (EOCV[7:0] * 512 = 0 .. 255*512)(可
配置开始时间
TM
19
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FXOSC
4-16MHz
FIRC
16MHz
div 1 to 32
FXOSC_DIV
FIRC_DIV
div 1 to 32
SYSCLK
System
Clock
Selector
(ME)
FMPLL
FIRC
FXOSC
32KHz
128KHz
CMU
SXOSC
SIRC
SXOSC
32KHz
div 1 to 32
SIRC
128KHz
div 1 to 32
div 1 to 16
Peripheral Set 1
div 1 to 16
Peripheral Set 2
div 1 to 16
Peripheral Set 3
FIRC_DIV
SXOSC_DIV
API / RTC
SIRC_DIV
FXOSC
FIRC
FMPLL
TM
RESET
SAFE
INT
Core
Platform
SWT
(Watchdog)
CLKOUT
Selector
20
div 1/2/4/8
CLOCK OUT
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Control SIRC state (ON/OFF) in STANDBY Mode. In all
other modes e.g. RUN, HALT, the SIRC is always ON(在
等待模式下控制SIRC状态。在所有模式下SIRC处于开状态)
•
Division factors ranging from 1, 2, 3....32(分频系数)
•
Trimming (+/- 2%)(微调)
TM
21
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FXOSC
4-16 MHz
FIRC
16 MHz
div 1 to 32
FXOSC_DIV
FIRC_DIV
div 1 to 32
SYSCLK
System
Clock
Selector
(ME)
FMPLL
FIRC
FXOSC
CMU
32 KHz SXOSC
SIRC
128 KHz
SXOSC
32 KHz
div 1 to 32
SIRC
128 KHz
div 1 to 32
div 1 to 16
Peripheral Set 1
div 1 to 16
Peripheral Set 2
div 1 to 16
Peripheral Set 3
FIRC_DIV
SXOSC_DIV
API / RTC
SIRC_DIV
FXOSC
FIRC
FMPLL
TM
RESET
SAFE
INT
Core
Platform
SWT
(Watchdog)
CLKOUT
Selector
22
div 1/2/4/8
CLOCK OUT
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
SXOSC 32KHz power down control and status
•
Division factors ranging from 1, 2, 3....32(分频系数)
•
Bypass mode(旁路模式)
•
Clock ready interrupt flag(时钟准备完成中断标志)
•
•
Configurable start-up time (EOCV[7:0] * 512 = 0 .. 255*512)(可配
置开始时间)
Not available on MPC5601/2D
TM
23
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Bit
Name
Description
11-15
LPRCTRIM
Trimming bits
19-23
LPRCDIV
Division factor
27
S_LPRC
SIRC Clock Status
31
LPRCON_STDBY
Control in STANDBY
mode
Note: The LPRCTRIM bits are programmed at the factory. They cannot be read, but if
you do a 32 bit write to the register to set the other configurable bits you will
OVERWRITE the original trim values. To configure those bits, perform a 16 bit write to
that section of the register instead.(LPRCTRIM有工厂默认配置,但是可以写入16位新
值)
TM
24
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FXOSC
4-16 MHz
FIRC
16 MHz
div 1 to 32
FXOSC_DIV
FIRC_DIV
div 1 to 32
SYSCLK
System
Clock
Selector
(ME)
FMPLL
FIRC
FXOSC
CMU
32 KHz SXOSC
SIRC
128 KHz
SXOSC
32 KHz
div 1 to 32
SIRC
128 KHz
div 1 to 32
div 1 to 16
Peripheral Set 1
div 1 to 16
Peripheral Set 2
div 1 to 16
Peripheral Set 3
FIRC_DIV
SXOSC_DIV
API / RTC
SIRC_DIV
FXOSC
FIRC
FMPLL
TM
RESET
SAFE
INT
Core
Platform
SWT
(Watchdog)
CLKOUT
Selector
25
div 1/2/4/8
CLOCK OUT
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
The purpose of the FMPLL is to generate a 64 MHz max (120
MHz target for Bolero 2M/4M) system clock from the FXOSC.
(FMPLL用来从FXOSC系统时钟产生64MHZ)
• The FMPLL operating modes(操作模式)
− Power
down(断电)
− Normal(普通)
− Normal with frequency modulation(普通频率调制)
− Progressive clock switching(步进时钟切换)
− 1:1
•
These modes are controlled by two registers(模式控制寄
存器)
− Control
Register (CR)(控制寄存器)
− Modulation Register (MR)(调制寄存器)
TM
26
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
•
The Mode Entry Module (MC_ME) provides SYSTEM modes and
USER modes (模式进入模块提供了系统和用户两种模式)
− SYSTEM:
RESET, DRUN (Default RUN), SAFE and TEST(系统模式)
− USER: RUN(0..3), HALT, STOP and STANDBY(用户模式)
•
For each mode the following parameters are configured/controlled:
(每种模式有下列参数进行配置和控制)
− System
clock sources (ON/OFF)(系统时钟源开关)
− System clock source selection(系统时钟选择)
− Flash power mode (ON, low power, power down)(Flash电源模式)
− Pad output driver state (Can disable Pad Output drivers, enabling high
impedance mode)(管脚输出状态,可以禁止或者高阻)
− Peripherals’ clock (gated/clocked)(外设时钟)
TM
28
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
User Modes用户模式
System Modes系统模式
SW request软件需求
Recoverable
RUN 0
HW failure可恢复硬件失效
Low Power
Modes低功耗模式
SAFE
HALT
RUN 1
RESET
DRUN
STOP
RUN 3
Non
recoverable
HW failure不可恢复硬件失效
TEST
STANDBY
HW triggered transition硬触发
SW triggered transition软触发
TM
29
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
RESET
− Completely
managed by hardware(完全硬件管理实现)
− The flash initialization is executed by hardware while device in
RESET(Flash在RESET时的初始化有硬件来完成)
•
DRUN (Default RUN默认RUN模式)
− Mode
automatically entered out of RESET or STANDBY(自动跳出
RESET和STANDBY)
− This mode is used by the application to configure the device out of
RESET or out of STANDBY(这个模式用于应用程序配置设备跳出
RESET或者STANDBY)
•
SAFE
automatically entered on “recoverable HW failure detection”
like oscillator, PLL or voltage failure(可恢复失效例如晶振,PLL失效)
− Device in a SAFE configuration with sysclk = FIRC & output at high
impedance (if configured so)(设备在安全模式配置下……)
− Mode
•
TEST
− Allow
device self tests like flash checksum, RAM BIST (自测闪存RAM)
TM
30
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
•
•
RUN[0..3]
−
Full performance available(RUN模式,所有特性使能)
−
Support WAIT instruction to stop the core with the capability to restart with very short latency (< 4 system clocks)(支持
WAIT指令停止核心,可以最快4个系统时钟恢复单片机)
HALT
−
Core stopped but system clock can remain the same as in RUN mode(核心停止,时钟保持)
−
Selective peripheral clock gating(可选择的外设时钟停止)
−
Flash can be put in low power mode(flash进入低功耗模式)
−
Useful to reduce device consumption during a slow serial communication, e.g. LIN frame transmission or reception(在较少
通讯时实用的减少设备功率消耗的方法,比如LIN)
−
Exit by interrupt, pin transition, or RTC/API timeout(中断退出,管脚传输或者时间中断)
STOP
−
•
Provides additional low power features beyond HALT, including:(提供比HALT更低功耗)

Clock to the core is disabled(core时钟禁止)

May be configured to switch off most of the peripherals(可以切断大多的外设)
STANDBY
−
Mode providing the lowest possible consumption(供给可能的最小功耗)
−
Most functions (digital and analog) of the device are not powered(大多功能仍旧保留)
−
Powers only the back-up logic (e.g. RTC/API, preserves wake-up inputs, part of SRAM)
−
On STANDBY exit, the processor uses the RESET vector or a SRAM Vector if enabled

−
WISR register in the Wake Up Unit can be used to verify the wake up source
Exit by RTC/API timeout or pin transition (退出机制)
TM
31
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Mode Enable Register (模式允许寄存器)
−
•
Mode Config Register (one for each mode)(模式配置寄存器)
−
−
•
Enable each peripheral to chose one of the 7 Run and LP Peripheral Control
Registers(使能外设运行在7种run和低功耗外设控制寄存器)
Mode Entry Control Register模式进入寄存器
−
−
•
Define which clocks are on/off in each mode for a peripheral(定义外设时钟源
开/关)
Peripheral Control register Register (0-143)外设控制寄存器
−
•
Define characteristics for each mode(定义每种模式的特性)
Voltage reg, Flash, FMPLL, FXOSC, FIRC on/off; which sysclock to use
Run/LP Peripheral Control Register (0-7)外设控制寄存器
−
•
Define which modes are allowed(定义那些模式允许)
Select mode and write key
Select mode and write inverse key
Mode Entry Global Status Register全局状态寄存器
−
Read mode transition status bit and wait until it clears读取状态寄存器直到清零
TM
32
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Each mode has a Mode Configuration register每种模式都有一个模
式配置寄存器
−
•
Example: ME_DRUN_MC
Key RUN mode configurations are circled:
0
1
2
3
4
5
6
7
reserved
16
17
18
19
20
21
22
23
8
9
PDO
reserved
24
25
PLL
ON
reserved
• PDO: Disable pad outputs (put in hi Z)
• MVRON: control VREG on/off
• CFLAON/DFLAON:
control code / data flash module
10
11
MVR
ON
26
27
OSC
ON
IRC
ON
12
13
DFLAON
28
14
15
CFLAON
29
30
31
SYSCLK
• PLLON: control PLL on/off
• OSCON: control XOSC on/off
• IRCON: control IRC16M on/off
• SYSCLK: select system clock
 Normal
 Low Power
 Power Down
TM
33
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
It is useful to keep a table of mode configurations used
•
Example below uses two USER modes. (Per AN2865 rev 4)
TM
34
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Modes must be enabled before entering them per the Mode
Enable register在进入模式前必须首先通过使能寄存器使能他们
• An interrupt is generated if attempt is made to enter disabled
mode如果没有使能的情况下进入会产生中断
TM
35
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S_CURRENT_Mode –
Current device mode status
0000 =RESET
0001 =TEST
0010 =SAFE
0011 =DRUN
0100 =RUN0
0101 =RUN1
0110 =RUN2
0111 =RUN3
1000 =HALT0
1010 =STOP0
1101 =STANDBY0
TM
S_PDO - Output power-down status specifies output powerdown status of I/Os. This bit is asserted whenever outputs of
pads are forced to high impedance state or the pad’s power
sequence driver is switched off.当IO输出成高阻态
S_MTRANS - Mode transition status模式转换状态
0 Mode transition process is not active转换没有开启
1 Mode transition is ongoing模式转换正在进行
S_DC - Device current consumption status设备功耗状态
0 = Device consumption is low enough to allow powering down
of main voltage regulator(设备功耗低至可以移除电压源)
1 = Device consumption requires main voltage regulator to
remain powered regardless of mode configuration(设备需要保
留电源
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MS_MVR - Main voltage regulator status
0 = Main voltage regulator is not ready
1 = Main voltage regulator is ready for use
S_DFLA - Data flash availability status
00 = Data flash is not available
01 = Data flash is in power-down mode
10 = Data flash is in low-power mode
11 = Data flash normal mode & available for use
S_FMPLL - FMPLL Locked Status
0 =FMPLL is not stable
1 = FMPLL is providing stable clock
F_FXOSC – Fast external crystal osc (4-16 MHz)
0 = Not stable
1= Stable
TM
S_ CFLA - Code flash availability status
00 =Code flash is not available
01 =Code flash is in power-down mode
10 =Code flash is in low-power mode
11 =Code flash is in normal mode and available for use
F_FIRC - Fast internal RC osc (16MHz)
0 = Not stable
1= Stable
S_SYSCLK - System clock switch status: Identifies
clock currently used by the system.
0000 =16 MHz int. RC osc.
0001 =div. 16 MHz int. RC osc.
0010 =4-16 MHz ext. XTAL osc.
0011 =div. ext. XTALl osc.
0100 =freq. mod. PLL
1111 = System clock is disabled
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Each peripheral can be associated with a particular clock
gating policy每个外设都可以和一个特殊时钟关断策略关联
• The policy is determined by two groups of peripheral
configuration registers:策略决定于两组外设配置寄存器
− ME_RUN_PC0:7
for RUN modes
− ME_LP_PC0:7 for Low Power modes
•
Clocks to peripherals are gated off unless enabled for that
mode 外设时钟处于关断状态,除非在那种模式下被使能
− Example
(per AN2865 rev 4):
TM
38
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Defines a selection of 8 possible RUN mode configurations for a peripheral定义
外设在RUN模式可能的8种配置
TM
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For each peripheral, there is a ME_PCTLx register to control clock gating
to that peripheral:每种外设都有一个仅存其用来控制时钟关断
- Selects one of the 8 Run peripheral set configurations
- Selects one of the 8 Low Power peripheral set configurations
- Enables/disables freezing the clock during debug
PERIPHERAL 143
PERIPHERAL 3
PERIPHERAL 2
PERIPHERAL 1
TM
40
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•
Software handled transition
−A
transition is requested writing a key protected sequence in ME_MCTL
− Mode Entry configures the modules according to the ME_xxx_MC
register of the target mode模式入口按照MExx寄存器所对应模式配置模
块
− Once all modules are ready, the new mode is entered所有模块就绪,新
模式进入
− Transition completion signalling: status bit/interrupt模式转换完成
− Note: Modification of a ME_xxx_MC register (even the current one) is
taken into account on next mode “xxx” entry寄存器配置在下次模式进入
生效
•
Hardware triggered transition硬件触发转换
− Exit
from low power mode从低功耗退出
− SAFE transition caused by hardware failure硬件失效导致的SAFE转换
− RESET transition caused by hardware failure硬件故障导致重启转换
TM
41
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Example: Peripheral Status Register 0范例:外设状态寄存器
−
Each bit indicates whether peripheral is frozen or active每个为对应外设状态
TM
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
RUN mode configurations allow(Run模式配置允许)
1.
Enabling/disabling system clock sources(使能/禁止系统时钟)
2.
Selecting appropriate system clock(选择合适的系统时钟)
3.
Gating clocks to peripherals(关断外设时钟)
•
Peripheral clocks can be divided as needed on a set basis
•
Example PLL: Initializing System Clock
TM
43
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Mode Enable Register 模式使能寄存器
−
•
Define which modes are allowed定义那种模式是允许的
Mode Config Register (one for each mode)模式配置寄存器
−
Define characteristics for each mode定义每种模式的特点
− Voltage reg, flash, FMPLL, FXOSC, FIRC on/off; which sysclock to use
•
Run/LP Peripheral Control Register (0-7)外设控制寄存器
− Define
•
which clocks are on/off in each mode for a peripheral
Peripheral Control register Register (0-143)外设控制寄存器
− Enable
each peripheral to chose one of the 7 Run and LP Peripheral
Control Registers
•
Mode Entry Control Register
− Select
mode and write key
− Select mode and write inverse key
•
Mode Entry Global Status Register
− Read
mode transition status bit and wait until it clears
TM
44
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
• Two elements to total power:所有功耗的两种特
征
−Dynamic Power
−Static Power
TM
– Run Current动态功耗
– Stop Current静态功耗
46
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Dynamic Power动态功耗
•
Basically caused by charging and discharging the gates of the
millions of MOS transistors and their interconnects. 基本上是由
于几百万的MOS管的开合充放电引起的
TM
47
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Current proportional to capacitance and switching speed
功耗和芯片的电容值和开关速度成正比
Smaller technology = Smaller transistors = Smaller gates
Smaller capacitances = Reduced power!
•
越小的三极管容值,功耗越小
Increased frequencies = Faster switching speeds
Larger currents = Increased power
•
芯片频率的升高导致功耗升高
Fortunately…the reduced capacitance wins out over the
faster switching speeds. 幸运的是容值减少的功耗大于频率
增加的功耗
Lower overall dynamic power
TM
48
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Static Power静态功耗
• Static leakage is a result of leakage current due to the finiteresistance of the off transistors between power and ground that exist
whenever power is applied
to a CMOS circuit. 漏电流
• Current is highly dependent on the
threshold voltage.电流严格受制于电压阀值
• As technology scales to ever smaller
dimensions, supply voltage levels are
likewise scaled. 工艺的改变促使电压水平相应改变
• To improve circuit speed, the threshold voltages are also decreased.
改善电路速度,电压阀值降低
• This decrease in threshold voltage results in an exponential increase
in the subthreshold leakage current !!!!电压阀值的降低导致相应的漏
电流指数级增长
• Becoming a much larger part of the total power equation!这成为总功
耗消耗的巨大组成部分
TM
49
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Static and Dynamic Power Trends (Frequency fixed)静态和动
态电流的趋势(频率一定情况下)
Power
Dynamic
Static
Technology shrinking
TM
50
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Trend for static power is up静态电流上涨
•
Even though dynamic power trends lower…increased requirements
for performance mean that the increased frequency offsets any
savings made through technology.纵然动态电流降低,增强的性能需
求使得频率增高,抵消了工艺改进的节省功耗
•
Overall…Power is going UP !总之,功耗上涨
TM
51
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
What can be done to “defy” physics?如何克服物理特性?
Clock management时钟管理
•
Ability to stop clocks on a per module basis停止模块时钟的能
力
•
Ability to divide down system clock to peripherals降速能力
On board clocking板级时钟
•
Part can self clock without PLL部分可以不需要PLL的自用时钟
•
16 MHz internal Osc
Power gating关断电源
•
Literally removing power to large areas of silicon逐步关断电源
TM
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
User Modes
Low Power
Modes
System Modes
Recoverable
HW failure
SW request
RUN 0
SAFE
HALT
RUN 1
RESET
DRUN
STOP
RUN 3
Non
recoverable
HW failure
TEST
STANDBY
HW triggered transition
SW triggered transition
TM
53
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
HALT
−
−
−
−
•
STOP
−
•
Core stopped but system clock can remain the same as in RUN mode
Selective peripheral clock gating
Flash can be put in low power mode
Useful to reduce device consumption during a slow serial communication, e.g. LIN frame
transmission or reception or providing PWM output
Provides additional low power features beyond HALT, including:

System clock can be disabled

PLL is always disabled
STANDBY
−
−
−
Mode providing the lowest possible consumption
Most functions (digital and analog) of the device are not powered
Powers only the back-up logic (e.g. RTC/API, preserves wake-up lines, part of SRAM)
There is no “pad keeper” function such as on MPC5510
 I/O other than wake-up lines go to high impedance, so external pullups/pulldowns may be needed

−
−
MPC560xB implements one standby mode: STANDBY0
On STANDBY exit, the processor uses the RESET vector or a SRAM vector if enabled

WISR register in the Wake Up Unit can be used to verify the wake up source
TM
54
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Key low power mode configuration controls are circled:
0
1
2
3
4
5
6
7
reserved
16
17
18
19
20
21
22
23
8
9
PDO
reserved
24
25
PLL
ON
reserved
• PDO: Disable pad outputs (put in hi Z)
• MVRON: control VREG on/off
• CFLAON/DFLAON:
control code / data flash module
10
26
OSC
ON
11
MVR
ON
27
IRC
ON
12
13
DFLAON
28
14
15
CFLAON
29
30
31
SYSCLK
• PLLON: control PLL on/off
• OSCON: control XOSC on/off
• IRCON: control IRC16M on/off
• SYSCLK: select system clock
 Normal
 Low Power
 Power Down
TM
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Peripheral Control Registers also specify peripheral clock gating policy for
low power by specifying one of 8 low power configuration registers
(ME_LP_PC0:7)
PERIPHERAL 143
PERIPHERAL 3
PERIPHERAL 2
PERIPHERAL 1
Example: 3 peripherals sharing a single low power peripheral configuation
TM
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Defines a selection of 8 possible LP mode configurations for
a peripheral
TM
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•
The MCU peripherals are allocated to various power domains
•
单片机外设分配了多个区域
•
The PCU allows users to remove or apply power to a power
domain depending on the operating mode允许用户移除加载在
某个区域的电源在相对应的操作模式下
Power Domain
Contains
0
Minimal circuitry for
low power, including
first 8 KB SRAM
Always ON
1
The rest of the
device except
SRAM
STANDBY: OFF
Other modes: ON
2
SRAM other than
the first 8KB SRAM
Configurable for
each mode
TM
58
State
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•
Each time the MCU changes mode, the PCU:
− Evaluates
the required status of each power domain
− Provides
controlled power-up or power-down of the power domain
(if required)
•
Only one power domain (2) can be controlled by the PCU
− Power
•
domains 0 and 1 are not controllable
A status register indicates the current state of each power
domain
TM
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
60
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
61
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Before entering low power mode:进入模式之前
− Configure
modes and peripherals (mode registers, peripheral control
registers)配置模式和外设(模式寄存器,外设控制寄存器)
− Transition
to RUN mode转换到RUN模式
− Configure
wake up pins (if necessary)配置唤醒管脚
− Configure
wake up timers (RTC/API)配置唤醒计数器
− Enable
wake up pins使能唤醒管脚
− Enable
wake up timers使能唤醒计数器
− Configure
where you will wake up (RGM_STDBY reg,
BOOT_FROM_BKP_RAM)配置唤醒源
•
Enter standby mode. (ME_MCTL. Target mode + key,
Target mode+ invkey)进入standby模式
TM
62
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•
PURPOSE: Reduce overall device power consumption
−
Power switching目的:减小总体外设功耗

Power can be saved by disconnecting parts of the device from the power
supply via a power switching可以通过开关移除外设电源

The device is grouped into multiple parts having this capability which are
called “power domains”外设可以被分成几个可关断区域来尽可能省电

When a power domain is disconnected from the supply, the power
consumption is reduced to zero in that domain当某个区域断电后可以减少
功耗

Any status information of such a power domain is lost当前区域的状态信息
消失

When re-connecting a power domain to the supply voltage, the domain
draws an increased current until the power domain reaches its operational
voltage重新连接该区域会逐步增加功耗直到加载的电压稳定
TM
63
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Power Control电源控制
− Power
domains are controlled on a device mode basis
− For each mode, software can configure whether certain power domains
are connected to the supply voltage (power-up state) or disconnected
(power-down state) (Power Domain 2 for Bolero)
− Maximum power saving is reached by entering the STANDBY0 mode
− On each mode change request, the MC_PCU evaluates the power
domain settings in the power domain configuration registers and
initiates a power-down or a power-up sequence for each individual
power domain
− The power-up/down sequences are handled by finite state machines to
ensure a smooth and safe transition from one power state to the other
STANDBY Mode
− Exiting the STANDBY0 mode can only be done via a system wakeup
event because all power domains other than power domain #0 are in
the power-down state
TM
64
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
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Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
RTC is a free running counter used for time keeping applications
−
Can generate interrupt independent of RUN or Low Power Mode
−
Can first generate a wakeup for low power exit, then interrupt
−
Continues counting through resets except for power up reset
Three selectable counter clock sources with optional prescalers:
−
SIRC (128 KHz)
−
SXOSC (32 KHz)
−
FIRC (16 MHz)
API provides regular timeouts for wakeup / interrupt
−
Compares lower 10 bits RTC to 10 bit compare value
−
At match, automatically adds programmed value for next compare
RTC provides longer timeout for wakeup / interrupt
−
Compares 12 bits above API to 12 bit compare value
TM
66
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
67
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
68
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
69
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
70
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
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names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
External wakeup/interrupt support with外部唤醒中断支持
−
−
−
−
−
−
−
Three system interrupt vectors for up to 18 interrupt sources for Bolero MPC5602/3/4B
Four system interrupt vectors for up to 24 interrupt sources for Bolero MPC5605/6/7B
Analog glitch filter per each wakeup line每个唤醒线路都有模拟错误滤波
Independent interrupt mask独立的中断屏蔽
Edge detection边沿侦测
Configurable system wakeup triggering from all interrupt sources
Configurable pull-up (recommended)可配置上拉
Non-maskable interrupt support with不可屏蔽中断支持
−
−
−
Edge detection边沿侦测
One NMI source with bypassable glitch filter一个不可屏蔽中断源并且支持旁路错误滤波器
Independent interrupt destination: non-maskable interrupt, critical interrupt,
or machine check request
On-chip wakeup support片上唤醒支持
−
−
Two wakeup sources (RTC and API)两个唤醒源
Wakeup status mapped to same register as external wakeup/interrupt status
TM
72
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•
The WKPU remains powered in low power mode
• Each pin can:唤醒单元在低功耗模式下保持开机状态
− Issue only a wakeup, or an interrupt, or both产生唤醒,中断
− Be sensitive on rising, falling or both edges对上升下降沿敏感
− Has an analog glitch filter, which can be separately enabled
− Internal pull-up内部上拉
In addition the chip
provides external interrupts
through different external
pins芯片提通过外部管脚供外
部中断
TM
73
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other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
•
Interrupt Vector 0
−
−
API
− RTC
PF[13], GPIO[93], E1UC[26], WKUP[16] (not
in 100-pin package)
−
PA[2], GPIO[2], E0UC[2], WKUP[3]
− PB[1], GPIO[17], CAN0RX, WKUP[4]
PG[3], GPIO[103], E1UC[12], WKUP[17] (not
in 100-pin package)
− PG[5], GPIO[105], E1UC[14], WKUP[18] (not
in 100-pin package)
−
PC[11], GPIO[43], CAN1RX, CAN4RX2, WKUP[5]
−
−
PE[0], GPIO[64], E0UC[16], CAN5RX2, WKUP[6]
−
PE[9], GPIO[73], CAN2RX3, CAN3RX2,
E0UC[23], WKUP[7]
−
PA[1], GPIO[1], E0UC[1], NMI, WKUP[2]
−
•
Interrupt Vector 2
•
PG[7], GPIO[103], LIN6RX, E1UC[16],
E1UC[30], WKUP[20] (on MPC5605/6/7B
only)
− PG[9], GPIO[105], LIN7RX, E1UC[18],
SCK_2, WKUP[21] (on MPC5605/6/7B only)
−
PB[10], GPIO[26], ANS[2], WKUP[8]
− PA[4], GPIO[4], E0UC[4], WKUP[9]
PA[15], GPIO[15], CS0_0, SCK_0, WKUP[10]
−
−
PB[3], GPIO[19], LIN0RX, SCL, WKUP[11]
− PC[7], GPIO[39], LIN1RX, WKUP[12]
PF[9], GPIO[89], CAN3RX, CAN2RX,
E1UC[1], CS5_0, WKUP[22] (on
MPC5605/6/7B only)
−
PI[3], GPIO[131], LIN9RX, E0UC[31],
WKUP[23] (on MPC5605/6/7B only)
− PI[1], GPIO[129], LIN8RX, E0UC[29],
WKUP[24] (on MPC5605/6/7B only)
−
PC[9], GPIO[41], LIN2RX, WKUP[13]
− PE[11], GPIO[75], LIN3RX, CS4_1, WKUP[14]
− PF[11], GPIO[91], WKUP[15] (not in 100-pin
package)
TM
Interrupt Vector 3 (on MPC5605/6/7B
only)
−
Interrupt Vector 1
−
PA[0], GPIO[0], E0UC[0], CLKOUT,
WKUP[19]
74
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•
Table shows wakeup
sources for 表格显示
唤醒源MPC5604B,
MPC5606S
•
Smaller packages do
not contain all ports
小封装可能不包含所
有
TM
75
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Name名称
Symbol
符号
Wakeup / Interrupt Status Flag
Register
WISR
Wakeup / Interrupt Rising-Edge
Event Enable Register
WIREER
Wakeup / Interrupt Falling-Edge
Event Enable Register
WIFEER
Interrupt Request Enable Register
Wakeup / Interrupt Filter Enable
Register
Wakeup / Interrupt Pull-up Enable
Register
Description目标
Flags event as defined by WIREER
and WIFEER
Enables rising-edge event
Enables rising-edge event
IRER
Enables flags to cause interrupt req.
WIFER
Enables analog glitch filter on
external pad input (filters glitch < 40
ns, passes signals > 1000 ns)
WIPUER
Enables pull-up on external pad (use
for all pads to minimize leakage)
NMI Configuration Register
NCR
Configuration settings for NMI
NMI Status Flag Register
NSR
Holds NMI status flags
TM
76
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Low power mode configurations allow power savings by低功耗配置允许通过
•
•
•
•
Turning the main voltage regulator on/off打开关闭主电压调节器
Putting the flash arrays in lower power将闪存进入低功耗
Disabling signal outputs to pads禁止信号输出到管脚
Providing a total power switch to most circuits using power
domains提供电源开关到所有的电源域
External input signals or internal timers can cause low power exit
• Typical values at room temp for Bolero 1.5M:室温下典型值
−
−
−
−
−
Run (64 MHz) = 70 mA
Halt = 8 mA
Stop = 250 µA
Standby (8k RAM) = 15-20 µA
Standby (32K RAM) = 30 µA
TM
77
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Before entering low power mode
− Configure
modes and peripherals (mode registers,
peripheral control registers)
− Transition
to RUN mode
− Configure
wake up pins (if necessary)
− Configure
wake up timers (RTC/API)
− Enable
wake up pins
− Enable
wake up timers
− Configure
where you will wake up (RGM_STDBY reg,
BOOT_FROM_BKP_RAM)
− Enter
standby mode (ME_MCTL. Target mode + key,
Target mode+ invkey)
TM
78
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
MPC5604B Starter Trak Board
User LEDs
Power Status
LEDs
USB
User buttons
Pot
MCU
TM
Pin Headers
80
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Steps
− Configure
modes and peripherals (mode registers, peripheral control
registers)
− Transition
− Setup
to RUN mode
pin to drive LED
− Configure
and enable RTC timer (RTC val = 27)
− Wait
for timeout
− Turn
LED on
− Configure
− Turn
and enable RTC timer (RTC val = 3)
LED off
− Configure
and enable RTC timer (RTC val = 27) ……..
TM
81
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Steps
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Configure modes and peripherals (mode registers, peripheral control registers)
Transition to RUN3 mode.
Configure Wake Up registers
Configure and enable RTC timer (RTC val = 27)
Enter STOP mode
On RTC timeout
Verify RUN3 is current mode
Configure pin to drive LED and turn on
Configure and enable RTC timer (RTC val = 3)
Enter STOP mode
On RTC timeout
Verify RUN3 in current mode
Turn LED off
Configure and Enable RTC timer (RTC val = 27) ……..
TM
82
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Steps
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Configure modes and peripherals (mode registers, peripheral control registers)
Transition to RUN3 mode
Configure Wake Up registers
Configure and enable RTC timer (RTC val = 27)
Enter STOP mode
On RTC timeout
Verify RUN3 is current mode
Configure pin to drive LED and turn on.
Configure and enable RTC timer (RTC val = 3)
Enter STOP mode
On RTC timeout
Verify RUN3 in current mode
Turn LED off
Configure and Enable RTC timer (RTC val = 27) ……..
TM
83
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
•
Thank you
Freescale on Kaixin
Tag yourself in photos
and upload your own!
Weibo?
Please use hashtag
#FTF2012#
Session materials will be posted @ www.freescale.com/FTF
TM
84
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM