1. No category

Politecnico di Milano
DRESD Project
OSyRiS
HOW TO PROVIDE A LINUX SUPPORT FOR
DYNAMIC RECONFIGURATION ON XILINX
FPGAS
Version 1.0
Ivan Beretta ivan.beretta@dresd.org
Giuseppe Mangano giuseppe.mangano@dresd.org
Marco D. Santambrogio marco.santambrogio@dresd.org
2008
CONTENTS
CONTENTS
Contents
1 Document License
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2 Introduction
2.1 Demo architecture and system requirements . . . . . . . . . .
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3 Synthesis of the architecture with ICAP
8
4 Compilation of Kernel and Modules
20
5 Starting the system
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6 Partial reconfiguration: a simple example
37
2
LIST OF FIGURES
List of Figures
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Open the Demo project . . . . . . . . . . . . . . . . . . . . . .
Open the system.xmp file . . . . . . . . . . . . . . . . . . . .
Our initial architecture (without ICAP) . . . . . . . . . . . . .
Copy ICAP into the demo/pcores folder . . . . . . . . . . . .
Rescan User Repositories . . . . . . . . . . . . . . . . . . . . .
Add the PLB to the architecture . . . . . . . . . . . . . . . .
Add the bridge to the architecture . . . . . . . . . . . . . . . .
Connect the bridge to the PLB and the OPB . . . . . . . . . .
Add ICAP to the architecture . . . . . . . . . . . . . . . . . .
Connect ICAP to the PLB . . . . . . . . . . . . . . . . . . . .
Filter by Addresses . . . . . . . . . . . . . . . . . . . . . . . .
Click the Generate Addresses button . . . . . . . . . . . . . .
Our final architecture (with ICAP) . . . . . . . . . . . . . . .
Toolbar buttons used to synthesize the final architecture . . .
Location of the generated bitstream . . . . . . . . . . . . . . .
The PetaLinux folder . . . . . . . . . . . . . . . . . . . . . . .
Edit system.mss . . . . . . . . . . . . . . . . . . . . . . . . . .
Vendor/Product selection in menuconfig . . . . . . . . . . . .
Select Customize Kernel Settings and Customize Vendor/User
Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hyper Terminal connection properties . . . . . . . . . . . . . .
Create a new iMPACT project . . . . . . . . . . . . . . . . . .
Select the JTAG option in iMPACT . . . . . . . . . . . . . . .
Ignore iMPACT’s Configuration File prompt . . . . . . . . . .
Assign a new Configuration File to the vc2vp30 device . . . .
Select download.bit as the bitstream to assign to the vc2vp30
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Click OK when the Object Files window appears . . . . . . .
Program the vc2vp30 device . . . . . . . . . . . . . . . . . . .
Click OK in the Programming Properties window . . . . . . .
At the end a Program Succeeded message will appear . . . . .
Either close iMPACT or choose the Disconnect All Cables option
Insert root as username and password at the login prompt that
appears in HyperTerminal . . . . . . . . . . . . . . . . . . . .
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1 DOCUMENT LICENSE
1
Document License
This work is licensed under a Creative Commons Attribution-Share Alike 2.5
Italy License1 .
You are free:
• to Share - to copy, distribute and transmit the work
• to Remix - to adapt the work
Under the following conditions:
• Attribution. You must attribute the work in the manner specified
by the author or licensor (but not in any way that suggests that they
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• Share Alike. If you alter, transform, or build upon this work, you may
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this one.
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terms of this work. The best way to do this is with a link to this web
page.
• Any of the above conditions can be waived if you get permission from
the copyright holder.
• Nothing in this license impairs or restricts the author’s moral rights.
1
http://creativecommons.org/licenses/by-sa/2.5/it/
4
1 DOCUMENT LICENSE
Abstract
This document describes how to implement an up and running
Linux-based system on the Xilinx Virtex-II Pro xc2vp30 FPGA board.
The architecture will be designed to enable internal partial reconfiguration support with an application developed at the MicroLAB (Politecnico di Milano - Italy).
Detailed steps will follow on how to build and synthesize the needed
architecture, configure and compile the kernel and software, and load
everything onto the board, using provided software and the Xilinx
Platform Studio. If you have any comments regarding this document
and/or if you’d like to help us in improving this material, please feel
free to get in touch with the authors.
5
2 INTRODUCTION
2
Introduction
An important feature provided by Xilinx Field Programmable Gate Arrays
(FPGAs [1]) which draws a lot of interest is the support for dynamic reconfiguration. Modern FPGAs provide partial dynamic reconfiguration capabilities, which allow the designer to reconfigure only part of the device,
while the remaining part is not affected and can continue its computation.
This ability can be exploited to execute different and independent hardware
applications on the same device at the same time, which can be added and
removed by configuring and removing them from the FPGA as they start or
complete.
The reconfiguration process is physically performed by writing the contents of a binary file called partial bitstream [2] on the FPGA, which contains
information to change the current configuration into the new one. In particular, reconfiguration is said to be internal when it is entirely performed
within the FPGA, which has to decide when a partial bitstream should be
configured, and where it can be retrieved, whereas external configuration is
managed by an external entity, such as a host machine.
The management of dynamic reconfiguration is generally performed by a
software application, which may be either a standalone code or an operating
system [3]. A standalone approach involves an application which relies on a
complete knowledge of the underlying hardware architecture (that over the
last years is constantly increasing together with the computational capabilities of FPGAs), and is limited by issues of portability and reusability of the
code. An operating system (OS) approach can support software multitasking
and provide a simplified interaction between user applications and IP-Cores
(Intellectual Property Cores - Xilinx’s independent modules) in the same
way a traditional OS manages the access to I/O peripherals. Since hardware
management is left to the operating system, which also simplifies the access
to hardware modules, software applications can rely on a high-level interface
which does not require the software developer to be aware of the hardware
architecture.
The software component of the platform used in this guide consists of the
µcLinux kernel2 , which has been ported to the MicroBlaze [4] processor. In
order to allow dynamic reconfiguration under Linux, a device driver has been
developed to provide an interface to an internal configuration interface called
Internal Configuration Access Port (ICAP) [5], which is used to physically
reconfigure most of the Xilinx FPGAs.
2
www.uclinux.org
6
2 INTRODUCTION
2.1
Demo architecture and system requirements
This guide describes how to load the µcLinux kernel onto the Xilinx University Program Virtex-II Pro Development System [6], which includes a
Virtex-II Pro xc2vp30 FPGA [7]. Moreover, a solution developed at MicroLab (Politecnico di Milano - Italy) is included in the kernel in order to
provide internal dynamic partial reconfiguration support. In the following
sections you will find detailed instructions on how to synthesize the architecture, compile the kernel and get the system up and running.
This guide is distributed with:
• A basic hardware architecture (for version 8.2 of Xilinx ISE [8] and EDK
[9]), which includes a general purpose processor, Ethernet and Serial
communication controllers, and memory units. The general purpose
processor used in this work is MicroBlaze (version 4.0.a), and the busbased communication among modules is implemented by the OPB bus
[10].
• The ICAP hardware controller, written in Verilog with a PLB-compatible
[11] interface.
• The source code of the ICAP device driver (with the Makefile needed
for the compilation).
• The source code of an additional application named ioctl.
To successfully complete all the steps described by this guide, you will need:
• Xilinx ISE and EDK 8.2.
• PetaLinux3 (in this guide we use version 0.30-rc1), which includes the
µcLinux kernel and a set of compiling tools.
• A Linux environment (in this guide we use CentOS 3.9 running on a
VMWARE virtual machine4 ).
µcLinux is a porting of the Linux kernel for micro controllers which do not
provide a hardware Memory Management Unit (MMU) module. Since version 4.0.a of the MicroBlaze processor does not include a MMU, the employment of µcLinux is required instead of the traditional Linux kernel. PetaLinux is a distribution which includes two µcLinux kernels (the 2.4.x and the
3
http://www.petalogix.com/
The installation of Linux on a VMWARE virtual machine is not covered in this guide.
For information regarding this procedure, please consult the official documentation available on VMWARE’s website: http://www.vmware.com/.
4
7
3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
2.6.x versions - the 2.4.x version is used in this guide), and a cross-compiler
to compile the kernel for the target MicroBlaze-based architecture.
3
Synthesis of the architecture with ICAP
In this section we will describe the steps necessary to create and synthesize
an architecture with the ICAP Controller for the VP30 board using the
Xilinx Platform Studio (in this section we use version 8.2i ) running on the
Windows XP operating system. At the end of this section we will obtain
the bitstream necessary to program the board. The demo folder contains
a Basic Architecture that has all the components necessary to get Linux
up and running on the VP30 board. The ICAP Controller, that is already
located in the plb icap top v1 00 a folder (therefore the Verilog sources
don’t need to be imported explicitly), will be added later on. To begin,
launch the Xilinx Platform Studio, choose the Open a recent project option,
the Browse for More Projects... option from the drop-down menu and click
OK (see Figure 1).
Figure 1: Open the Demo project
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
In the new Open Existing Project window, browse to the demo folder and
open the system.xmp file (see Figure 2).
Figure 2: Open the system.xmp file
Moments later, we are presented with our initial architecture (that can
be viewed and modified in the System Assembly View), in which the ICAP
Controller is not yet present (see Figure 3).
Figure 3: Our initial architecture (without ICAP)
The only Software Project that will be loaded on the BRAM (it is placed
in this memory bank because it has to be executed first) is microblaze 0 bootloop
(the others are disabled). This program will make the system remain in
standby, awaiting the kernel.
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
At this point, the plb icap top v1 00 a folder must be copied into the
demo/pcores folder (see Figure 4).
Figure 4: Copy ICAP into the demo/pcores folder
Once this is done, from the Project dropdown menu, choose Rescan User
Repositories (see Figure 5).
Figure 5: Rescan User Repositories
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Now that the project is based on the MicroBlaze processor, that doesn’t
support the PLB bus out-of-the-box. Therefore, we must add it to the project
and connect it to the OPB bus (that is already present). To add the PLB
bus, in the Project Information Area, under the IP Catalog tab, expand the
Bus group, select one of the two PLBs available (either one will do; in the
example, we choose plb v34 - version 1.01.a) and performing a drag-and-drop
operation, add it to the other components of the architecture (see Figure 6).
Once this is done, the PLB will appear in the System Assembly view.
Figure 6: Add the PLB to the architecture
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Now we need a bridge between the OPB and the PLB, so that the MicroBlaze processor can connect to the PLB and communicate with the ICAP
Controller (that will be connected to the PLB). To add the bridge, in the
Project Information Area, under the IP Catalog tab, expand the Bus Bridge
group, select opb2plb bridge, and performing a drag-and-drop operation, add
it to the other components of the architecture (see Figure 7). Once this is
done, the bridge will appear in the System Assembly view.
Figure 7: Add the bridge to the architecture
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Now the bridge must be connected to the PLB (as master) and the OPB
(as slave). To do this, expand the new opb2plb bridge 0 component that just
appeared and edit the bus connections of SOPB (slave) and MPLB (master).
Using the dropdown menus, assign mb opb as the Bus Connection of SOPB
and plb v34 0 as the Bus Connection of MPLB (see Figure 8).
Figure 8: Connect the bridge to the PLB and the OPB
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Now we can add the ICAP Controller. In the Project Information Area,
under the IP Catalog tab, expand the Project Repository group, select plb icap top
(that was added to the list when we performed the Rescan User Repositories)
and performing a drag-and-drop operation, add it to the other components
of the architecture (see Figure 9). Once this is done, the ICAP Controller
will appear in the System Assembly view.
Figure 9: Add ICAP to the architecture
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Now the ICAP Controller must be connected to the PLB. To do this,
expand the new plb icap top 0 component that just appeared and edit the
bus connection of SPLB (slave). Using the dropdown menus, assign plb v34 0
as the Bus Connection of SPLB (see Figure 10).
Figure 10: Connect ICAP to the PLB
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Once this has been done, we need to generate an addressing space for
the new components we have just added. ICAP’s address range must be
included in the bridge’s, because when the MicroBlaze processor requests
ICAP’s address on the OPB bus, the bridge will recognize and forward said
request to the PLB bus, so that it reaches ICAP. Therefore, the bridge must
answer to all the addresses of the devices located on the PLB bus and forward
the requests. To do so, in the System Assembly View, under Filters, select
Addresses, and you will be presented with the following view (see Figure 11):
Figure 11: Filter by Addresses
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
At this point, clicking on the Generate Addresses button, the Base Address and High Address of both the bridge and ICAP will be created (see
Figure 12):
Figure 12: Click the Generate Addresses button
It is important that you take note of the Base Address that has just been
generated for ICAP (in our case: 0xcd400000), because we will need this
value in Section 4.
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Now the MicroBlaze processor can connect to ICAP, and we have obtained our final architecture, that we can view changing the filter back to
Bus interface (see Figure 13).
Figure 13: Our final architecture (with ICAP)
To synthesize our architecture, using the toolbar, launch in this order the
following operations: Generate Netlist (1), Generate Bitstream (2), Generate
Libraries and Drivers (3), Build All User Applications (4), Update bitstream
with software program information (5) (see Figure 14).
Figure 14: Toolbar buttons used to synthesize the final architecture
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3 SYNTHESIS OF THE ARCHITECTURE WITH ICAP
Once these last steps are performed, the bitstream (download.bit), that
contains also our bootloop (the first thing that will be executed on the board)
will appear under the demo/implementation folder (see Figure 15), ready to
be used to configure our board.
Figure 15: Location of the generated bitstream
19
4 COMPILATION OF KERNEL AND MODULES
4
Compilation of Kernel and Modules
This section explains how to create the Kernel that will be loaded on the
VP30 board using the JTAG interface. To begin, we will need to generate a
configuration file with EDK. This file contains information needed to build
a working kernel on the hardware architecture that we have synthesized in
Section 3. To obtain our Kernel (version 2.4) we will need PetaLinux (in this
guide we use version 0.30-rc1), that already contains scripts to import the
configuration file into the correct folder. The Kernel compilation should be
performed inside a Linux environment that is as similar as possible to RedHat
(because the Xilinx tools were designed to work seamlessly with this flavour
of Linux). The Linux environment can be run on a virtual machine, with a
loss of performance as the only significant drawback. The hardware synthesis
is so processor-intensive that it is best to perform said operation on a nonemulated system, like we did in Section 3 (on Windows XP). This tutorial
uses CentOS (Community Enterprise Operating System) version 3.9, running
on a VMWare virtual machine. On it we have installed the Xilinx Platform
Studio to the default folders. More detailed instructions on how to install
PetaLinux in the Linux Environment can be obtained visiting the official
website (www.petalogix.com). From the Petalogix website the PetaLinux
compressed file (in our case petalinux-v0.30-rc1.tar.gz ) must be downloaded
and its contents extracted. As root (the account that we used through this
whole section) we extracted the contents of the compressed file to the /root
folder. Doing this, we have obtained the /root/petalinux-v0.30-rc1 folder (see
Figure 16).
Figure 16: The PetaLinux folder
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4 COMPILATION OF KERNEL AND MODULES
This folder contains important files and folders such as the settings.sh
script (that defines the environment variables), the hardware folder (that
contains all the hardware architectures that the system will be compiled on),
the tools folder (that contains cross-compilers and scripts) and the software
folder (that contains the linux kernel sources and various applications). We
have already synthesized our hardware (following the steps of Section 3); now
we have to generate all the definitions needed to compile correctly the kernel,
such as the addresses of every peripheral and the memory sizes. To begin,
open a console, enter the petalinux-v0.30-rc1 folder, and input the following
command to set the environment variables:
source settings.sh
If done correctly, the output of the command should be:
PetaLinux environment set to ’/root/petalinux-v0.30-rc1’
Now, always using the console, enter the Xilinx folder and perform the
same operation two more times: in the folder where ISE is installed (by
default: Xilinx/ISE ) and in the folder where EDK is installed (by default:
Xilinx/EDK )
cd ISE
source settings.sh
cd ../EDK
source settings.sh
This time, no output should be expected. It is important that the environment variables are set every time the console is opened.
Once this is done, copy the demo folder into the petalinux-v0.30-rc1/hardware/userplatforms folder (obtaining the new directory structure petalinux-v0.30-rc1/hardware/userplatforms/demo/ ). Enter the newly created demo folder. Now we have to
make EDK generate the file needed to configure correctly our Linux version.
When EDK has to generate the libraries for the stand-alone mode it already
knows what folders to access, but when we give instructions to use PetaLinux, by default it searches for them in the edk user repository folder. This
folder exists, but not in the project folder, therefore we need to create a
symbolic link in the main directory of the project:
ln -s ../../edk_user_repository/ edk_user_repository
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4 COMPILATION OF KERNEL AND MODULES
Now we can launch EDK from the console with the xps command (that
stands for Xilinx Platform Studio). The .mss files specify for each hardware component what drivers should be used, the library version, and other
information. We will need to edit the .mss file to change the destination
from stand-alone mode to PetaLinux mode, making EDK search for all the
device drivers of the operating system in the edk user repository folder. As
described in Section 3 (see Figure 1), choose the Open a recent project option, the Browse for More Projects... option from the drop-down menu and
click OK. In the new Open Existing Project window, browse to the petalinuxv0.30-rc1/hardware/user-platforms/demo/ folder and open the system.xmp
file. When we created the architecture under Windows (see Section 3), it
was generated stand-alone by default. To edit system.mss, under the Project
tab, expand the Project Files group and open the file. The PARAMETER
VERSION and the OS group must be edited to:
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER
PARAMETER
PARAMETER
PARAMETER
PARAMETER
PARAMETER
PARAMETER
PARAMETER
END
OS_NAME = petalinux
OS_VER = 1.00.b
PROC_INSTANCE = microblaze_0
1mb_memory = dlmb_cntrl
main_memory = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
stdin = RS232_Uart_1
stdout = RS232_Uart_1
main_memory_bank = 0
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4 COMPILATION OF KERNEL AND MODULES
Now that this is done (see Figure 17), EDK can generate the configuration
file (auto-config.in) for the Kernel using the Generate Libraries and Drivers
button of the EDK toolbar (number 3 of Figure 14).
Figure 17: Edit system.mss
At this point, the auto-config.in has been created in the petalinux-v0.30rc1/hardware/user-platforms/demo/microblaze 0/libsrc/petalinux v1 00 b/ folder.
Now we have to create a platform with all the peripherals and addresses that
we have designed. With the console, from the petalinux-v0.30-rc1/hardware/userplatforms/demo/ folder, launch the command:
petalinux-new-platform -k 2.4 -v Prova -p Micro
With the -k option we specify the kernel version; with -v and -p we specify
the vendor and platform information (these last two parameters can be set
to anything you like).
If done correctly, the output of the command will be:
New platform for Prova Micro successfully created
Now, enter the the software-side folder and launch the make menuconfig
command:
cd ../../../software/petalinux-dist/
make menuconfig
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4 COMPILATION OF KERNEL AND MODULES
When the Main Menu appears, in the Vendor/Product Selection section,
we set (in our case) Prova as Vendor and Micro as Product (see Figure 18).
Figure 18: Vendor/Product selection in menuconfig
Now select Exit to navigate back to the Main Menu, select Exit again
to exit menuconfig and select Yes when asked if we want to save our new
Kernel configuration (WARNING: if a .config file already exists it will be
over-written!). At this point we have the desired platform, but it is empty;
we have to go back to the hardware-related folder of the project and launch
the petalinux-copy-autoconfig command to associate the auto-config.in file we
created earlier with this platform:
cd ../../hardware/user-platforms/demo/
petalinux-copy-autoconfig
If done correctly, the output of the command will be:
INFO: Attempting vendor/platform auto-detect
INFO: Auto-detected Prova/Micro combination.
Auto-config file successfully updated for Prova Micro
At this point we can go back to the Kernel folder to configure and compile
it:
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4 COMPILATION OF KERNEL AND MODULES
cd ../../../software/petalinux-dist/
make menuconfig
Enter the Kernel/Library/Defaults Selection section and select the options Customize Kernel Settings and Customize Vendor/User Settings (see
Figure 19).
Figure 19: Select Customize Kernel Settings and Customize Vendor/User
Settings
Now select Exit to navigate back to the Main Menu, select Exit again
to exit menuconfig and select Yes when asked if we want to save our new
Kernel configuration. Once the Main Menu appears again, edit the following
options:
[ENABLE]
Loadable module support --->
Set version information on all module symbols
[ENABLE]
Loadable module support --->
Kernel module loader
[DISABLE]
Memory Technology Devices (MTD) --->
RAM/ROM/Flash chip drivers --->
Detect flash chips by Common Flash Interface (CFI) probe
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4 COMPILATION OF KERNEL AND MODULES
[DISABLE]
Memory Technology Devices (MTD) --->
Detect JEDEC JESD21c compatible flash chips
[set: NONE] Memory Technology Devices (MTD) --->
Mapping drivers for chip access ---> FLASH size
[ENABLE]
File systems --->
/dev file system support (EXPERIMENTAL)
The Kernel module loader is needed to load the ICAP device driver (this
operation will be performed in section 5). The FLASH size must be set to
NONE because at compile time some MACROs that define the size of the
FLASH are missing. Now exit the Main Menu and select Yes when asked if
we want to save our new Kernel configuration. The Main Menu will appear
again, to allow us to customize the applications, but unless you have specific
needs, no further modifications are needed, so we can exit once more the
Main Menu (selecting Yes when asked if we want to save our new Kernel
configuration).
Once this is done, we can compile and/or add to the filesystem the programs and files that we will need on the board when the system is up and
running. In our case, we will compile the ICAP device driver, generate ioctl
(a simple application that performs generic I/O operations on the ICAP device), and also add a partial bitstream5 . To begin, we copy the icap and ioctl
folders (included with this guide) to the petalinux-v0.30-rc1/software/userapps/ folder.
Now that ICAP’s device driver writes directly to memory, we must open
the icap/icap globals.h file and edit the definition of ICAP’s Base Memory
address. In our case (see Figure 12), the line will become:
#define ICAP_BASE
0xCD400000
Then, using the console, we enter the icap folder and type the make
command to compile ICAP:
cd icap/
make
Of all the object-code files that are generated with the compilation, the
only one that we will need is icap.o, that will be dynamically linked in the
kernel. At this point, we enter the ioctl folder and compile it:
5
The generation of partial bitstreams is not covered in this guide. Some information
regarding this procedure can be found in Xilinx’s XAPP290 guide [12].
26
4 COMPILATION OF KERNEL AND MODULES
cd ../ioctl/
make
The only file that we will need is the ioctl binary (without any extension)
that has just been created.
On a side note, to create your own programs (for example one called
myprogram), you can enter the following command from the petalinux-v0.30rc1/software/user-apps/ folder:
petalinux-new-app myprogram
If done correctly, the following output will be displayed:
New application template successfully created in software/user-apps/myprogram
See myprogram/README for what to do next.
At this point, you can enter the newly-created myprogram folder, edit the
myprogram.c template that has been generated and eventually compile your
new program.
Now we have make sure that the files we need will be present in the
board’s filesystem (icap.o, ioctl and diff.bit). Anything we copy to the romfs
folder (that contains the filesystem structure to be merged with the kernel)
will be present on the FPGA board, therefore we can input the following
commands:
cp $PETALINUX/software/user-apps/icap/icap.o
$PETALINUX/software/petalinux-dist/romfs/usr
cp $PETALINUX/software/user-apps/ioctl/ioctl
$PETALINUX/software/petalinux-dist/romfs/bin
cp /mnt/pendrive/diff.bit
$PETALINUX/software/petalinux-dist/romfs/usr
Once this is done, always from the console, return to the /software/petalinuxdist/ folder and run the following commands compile the Kernel:
make
If done correctly, the new images folder will appear, containing important
files such as linux.bin (the Kernel image), romfs.img (the filesystem image)
and image.bin (the combination of the Kernel and the filesystem), all of
which have been cross-compiled for MicroBlaze. This last file (image.bin) is
the one that we load on the VP30 board.
27
5 STARTING THE SYSTEM
5
Starting the system
Now that we have the bitstream (download.bit) and the Kernel+filesystem
(image.bin), we can program the FPGA, load the Kernel and launch the
system. We will use HyperTerminal to access the console once the system is
up, iMPACT (a tool of ISE) to program the board and the Xilinx debugger
(XDM ) to load the Kernel. First, connect all the cables (serial, JTAG, power
cable) to the board and switch it on. Next, in Windows XP, open HyperTerminal (Start - Programs - Accessories - Communications - HyperTerminal),
that we will use to interact with our system, after it boots up, via console. If
the Location Information window appears, you can click Cancel, but filling
in the requested information will prevent future prompts.
Now you can enter any name in the Connection Description window that
appears and click OK. Once the Connect To window appears, edit the Connect using option selecting the COM (serial) of the PC that you are using to
connect to the board and click OK. The only options that need to be edited
are Bits per second, that must be set to 9600, and Flow control, that must
be set to None (see Figure 20).
Figure 20: Hyper Terminal connection properties
28
5 STARTING THE SYSTEM
The terminal must be left open, and will remain blank until we load the
Kernel onto the board. Now we must use iMPACT (Start - Programs - Xilinx
ISE 8.2i - Accessories - iMPACT) to program the board with the bitstream.
Once it has started, select create a new project (.ipf ) in the iMPACT Project
window that appears and click OK (see Figure 21).
Figure 21: Create a new iMPACT project
In the new window that appears, click Finish accepting the default option:
Configure devices using Boundary-Scan (JTAG) (see Figure 22).
Figure 22: Select the JTAG option in iMPACT
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5 STARTING THE SYSTEM
Now click Cancel All in the new window that appears (see Figure 23).
Figure 23: Ignore iMPACT’s Configuration File prompt
We are presented with 3 devices. Right-click on the third one (vc2vp30 )
and select Assign New Configuration File... from the menu (see Figure 24).
Figure 24: Assign a new Configuration File to the vc2vp30 device
30
5 STARTING THE SYSTEM
In the new Assign New Configuration File window that appears, navigate
to the demo/implementation folder, select the download.bit bitstream and
click Open (see Figure 25).
Figure 25: Select download.bit as the bitstream to assign to the vc2vp30
device
When the new Add Virtex-/II Pro/Virtex 4 Object Files window appears,
simply click OK (see Figure 26).
Figure 26: Click OK when the Object Files window appears
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5 STARTING THE SYSTEM
Now right-click again on the (vc2vp30 ) device and select Program... from
the menu (see Figure 27).
Figure 27: Program the vc2vp30 device
When the new Programming Properties windows appears, click OK (see
Figure 28).
Figure 28: Click OK in the Programming Properties window
32
5 STARTING THE SYSTEM
If done correctly, after the Progress Dialog window disappears, a Program
Succeeded message will appear (see Figure 29), and the red DONE led on
the board will turn on.
Figure 29: At the end a Program Succeeded message will appear
Now that the serial port is still locked, it is important that you release it
either closing iMPACT or selecting Disconnect All Cables from the Output
dropdown menu (see Figure 30).
Figure 30: Either close iMPACT or choose the Disconnect All Cables option
At this point, the bootloop is active on the board and awaiting the Kernel.
We will therefore use the debugger to upload it and edit the Program Counter
so it runs the first instruction present at the address where the Kernel begins.
To do so, create a new folder and copy inside it our image.bin file. Then,
create inside the folder a New Text Document (right-click inside the folder
- New - Text Document). Now, open New Text Document.txt and write the
following lines:
33
5 STARTING THE SYSTEM
01
02
03
04
05
06
07
08
connect mb mdm
dow -data image.bin 0x30000000
puts " *** Download completed! *** "
mwr 0x100 0
rwr 5 0x100
rwr pc 0x30000000
con
puts " *** Starting system... *** "
Line 01 connects the debugger to the MicroBlaze processor through the
debugging interface. Line 02 loads image.bin onto the board, starting at
memory address 0x30000000. The 3 instructions (04, 05 and 06) right after
the line that displays the Download Completed! message change the value
of the Program Counter to 0x30000000, where image.bin has been copied,
and enable the system to resume its execution from this new memory address. Then, with line 07, the script executes the con command, that makes
the bootloop continue its execution from the new program counter value.
Finally, the Starting System... message will be displayed. Once New Text
Document.txt has been edited and saved, it must be renamed to xmd.ini.
Now proceed to launch the debugger (Start - Programs - Xilinx Platform
Studio 8.2i - Accessories - Launch EDK Shell). Once it is ready, navigate to
the folder you have just created (using Linux console commands) and launch
the debugger with the xmd command, that will immediately check for (and
run) the xmd.ini script we have created.
34
5 STARTING THE SYSTEM
A boot sequence will start in the HyperTerminal window (that we had
left open), and when it completes a login prompt will appear. The default
username is root, with root as password (see Figure 31).
Figure 31: Insert root as username and password at the login prompt that
appears in HyperTerminal
To view a list of available commands, you can type help. To add the
ICAP device and load its module, you must enter the following commands:
mknod /dev/icap c 120 0
insmod /usr/icap.o
If done correctly, the following output will be displayed:
Using icap.o
icap: Xilinx Virtex-II FPGA ICAP driver v. 0.2 (2.4.32-uc0)
Written by Alberto Donato <donato@elet.polimi.it>
Now the system is ready to be used. You can load and use a partial
bitstream (in this example we load diff.bit) with the following commands:
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5 STARTING THE SYSTEM
cat /usr/diff.bit > /dev/icap
ioctl /dev/icap c 2
The cat command memorizes the bitstream in a memory area allocated
by the device driver, making it ready to be used when the reconfiguration is
requested. To free said memory you can use the ioctl /dev/icap c 1 command.
36
6 PARTIAL RECONFIGURATION: A SIMPLE EXAMPLE
6
Partial reconfiguration: a simple example
We where trying to find the best way to end this document and we finally
agree that the best way was to provide a very simple example for the partial
reconfiguration. Designing a complete partial reconfigurable architecture was
out of the scope of this document, we will provide soon a second tutorial with
all this information.
If you’d like to try this very simple example, you will find all the necessary
files (download.bit, diff.bit, image.bin) intoBinaries directory. download.bit
is the startup bitstream file, while image.bin will allow you to run the software part of this example. Once you’ll have the Linux-based system up and
running onto your FPGA you can load and use a partial bitstream (in this
example we load diff.bit) with the following commands:
cat /usr/diff.bit > /dev/icap
ioctl /dev/icap c 2
As a result you should be able to see on of your led to switch off. The cat
command memorizes the bitstream in a memory area allocated by the device
driver, making it ready to be used when the reconfiguration is requested.
37
REFERENCES
References
[1] S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Fieldprogrammable gate arrays. Norwell, MA, USA: Kluwer Academic Publishers, 1992.
[2] S. Corbetta, F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio,
and D. Sciuto, “Two novel approaches to online partial bitstream relocation in a dynamically reconfigurable system,” VLSI, 2007. ISVLSI
’07. IEEE Computer Society Annual Symposium on, pp. 457–458, March
2007.
[3] A. Donato, F. Ferrandi, M. Redaelli, M. D. Santambrogio, and D. Sciuto,
“Exploiting partial dynamic reconfiguration for soc design of complex
application on fpga platforms.” pp. 87 – 109, 2007.
[4] Xilinx, Inc., “MicroBlaze processor reference guide,” June 2007.
[5] Xilinx, “Opb hwicap (v1.00.b) product specification,” March 2005.
[6] Xilinx, Inc., “Xilinx University Program Virtex-II Pro development system hardware reference manual,” April 2008.
[7] Xilinx, “Virtex-II Pro and Virtex-II Pro platform FPGAs: Complete
data sheet,” November 2007.
[8]
[9]
[10] IBM, “On-Chip Peripheral Bus architecture specifications,” April 2001.
[11] IBM, “128-bit Processor Local Bus architecture specifications,” May
2007.
[12] Xilinx, Inc., “Difference-based partial reconfiguration, Tech.
Rep.
XAPP290,
December
2007.
[Online].
Available:
http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf
38