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Great River Technology, Inc.
Jan 26, 2001
6121 Indian School Rd NE
Suite 141
Albuquerque, NM 87110
Phone: 505-881-6262
email: tkeller@greatrivertech.com
Fax: 505-883-1375
RE: GRTQ_111021-1 Rev A
October 25, 2011
Attn:
Sunny Lee
SungWha Tech,
701, Hongin Officetel, Bongmyung-dong, Yusung-gu,
Daejeon City, 305-710, South Korea
Tel: +82 42 828 7857
Email: info@sungwhatech.com
From:
Tim Keller
Director of Marketing
505 881 6262
Discussion and Statement of Work
SungWha Tech has requested a quote for an ARINC 818 IP core.
GRT’s ARINC 818 IP core is built by engineers with more than 10 years experience developing FCAV and ARINC 818 systems for top aerospace companies, including: Boeing, Airbus, Rockwell
Collins, Honeywell, Thales, Lockheed Martin and many others. Working with GRT and using our
ARINC 818 IP Core will save many months of engineering and will typically reduce your
implementation cost by more than 60%. When you work with GRT, you will have direct access to
engineers that are the world’s top experts in ARINC 818. GRT has developed and customized
ARINC 818 products for more than 30 companies around the world.
ARINC 818 is a high speed video protocol standard titled Avionics Digital Video Bus, it is the video
protocol selected for major new aerospace platforms, including: the Airbus A400M military
transport, the Airbus A350XWB, and the Boeing 787. ARINC 818 is also used in military
applications as a camera (sensor) interface and a video backbone for all cockpit displays (C130AMP; F/A 18 F).
Additional information on ARINC 818 can be found at www.arinc818.com.
1 IP Core Description
Great River Technology offers a flexible ARINC 818 IP core. The core can be configured at
compile time for different video parameters and pixel packing methods. The flexible core is
appropriate for lab and development work, but for systems that will be certified, the core will
be pre-configured to match the desired video parameters. Pre-configuring the core will
reduce the validation and certification effort.
1
Great River Technology’s (GRT) ARINC 818 transceiver core provides an easy way to
implement ARINC 818 compliant interfaces in Xilinx V5, V6, Spartan 6, Altera Stratix II, IV
GX and ARRIA PLDs. The core uses Xilinx Rocket IO transceivers (MGTs or GTP tiles) to
achieve ARINC 818 interfaces up to 4.25 Gbps. The core can be used for transmit only,
receive only, or for transmit and receive applications.
The core has many flexible compile time settings allowing for various link speeds, line
segmentations, and line synchronization methods. The core can be configured for various
resolutions and pixel packing methods. Ancillary data can use default values set at compile time or
data can be updated in real time via register interface.
Features

Supports link speeds up to 4.25 Gbps
Compatible with most video resolution/frame rates
Compatible with progressive and interlaced video
Simple pixel bus transmitter interface
Configurable for various pixel packing and input formats
Supports line synchronous transmission
Embedded default ancillary data or real time update
Compatible with in Xilinx and Altera PLDs
Configurable for various line segmentations
Receiver error and status detection
Complete Header/Ancillary data recover
Block Diagrams
The transmitter has a simple interface where native Vsync, Hsync, and pixel clocks can be used.
Out-going ARINC 818 frames are governed by this input timing. Internal FIFOs allow writing of
continuous line data without hold off, therefore, the core can be tied directly to pixel buses with
various timings (such as VESA timings). The core supports various color input formats (up to 32-bit
RGBA) and monochrome formats (up to 16-bits). Internal pixel packing logic can be configured to
compress data prior to transmission.
tx data in
tx pixel clk
tx we
Pixel
Packing
FIFO
Flags
ADVB
Framing
State
Machine
CRC
Calc
tx vsync
Transceiver
Interface
FC
Data
Sync
Control
tx hsync
RIO
MGT
Serial
or
GX
A818 Transmitter
The receiver is configurable for unpacking pixel data in several formats. The PLD interface is a 32bit wide data bus with a simple data valid signal. The core has internal receiver FIFOs so that the
Pixel clock rate can be set by the user.
rx pixel clk
Serial
RIO
MGT
FC Data
Transceiver
Interface
or
GX
A818 Receiver
FIFO
Data
recovery
State
Machine
CRC
and status
Pixel
unpack
rx data out
rx data val
rx obj0 val
Status
2
Deliverables:
VHDL and Encripted VHDL files
Instantiation templates
VHDL test bench
UCF file templates
Coregen output files
User’s Guide
Optional Aerospace Certification Package
Optional Chipset and Reference Design
2 Certification Support and Documentation Package
GRT is developing a DO-254 DAL A certifiable package for the ARINC 818 IP Core. The goal of the
package will be that customers need only test the IP core as a “black box”, and the can rely on
GRT’s life cycle data. This process will greatly simplify the customer’s certification effort.
The ARINC 818 IP Core for DO-254 certification will become a single component in the customer's
(or end-user's) airborne electronic hardware, where it will co-exist with other logic circuits within an
FPGA.
The customer will be responsible for the certification effort for this airborne hardware, using his own
hardware life cycle processes. To the greatest degree practical, GRT’s IP Core product will
anticipate the needs of the customer, and will pre-package design artifacts to support an expected
(or typical) end-user life cycle program.
To realize such a product package, GRT is developing the IP core product within the framework of
DO-254. This will be conducted to the greatest degree practical; in light of the fact that aircraft level
requirements will be missing.
The table below shows the artifacts that will be generated and available to the DER and the
customer.
Hardware Design Life Cycle Data
ARINC 818 IP Core
Data Item
ARINC 818 IP Core Design
Assurance Plan
IP Core Configuration Management
Plan
GRT ARINC 818 Standards Review
Checklists
ARINC 818 IP CORE Requirements
Specification
ARINC 818 IP Core Conceptual
Design Document
ARINC 818 IP Core Design
Specification
VHDL Coding Standard Document
ARINC 818 IP Core VHDL Source
DER
Availability
Yes
Customer
Deliverable
Yes
Yes
Customer
SOI
Support
DO-254 Objective
1
4.1(1,2,3,4); 6.1.1(1); 7.1(3)
Yes
1
4.1(1,2,3,4); 6.1.1(1); 7.1(3)
Yes
Yes
1, 2
4.1(2);5.5.1(1);7.1(1,2)
Yes
Yes
2, 3
Yes
Yes
2, 3
5.1.1(1,2); 5.2.1(2); 5.3.1(2); 5.4.1(3);
5.5.1(1,2,3);
6.1.1(1,2); 6.2.1(1)
5.2.1(1)
Yes
No
2, 3
5.3.1(1); 5.4.1(2)
Yes
Yes
No
No*
2, 3
5.3.1(1); 5.5.1(1) 4.1(1,2,3,4); 7.1(3)
3
Code/constraints
ARINC 818 IP Core Test Procedures
Document
ARINC 818 IP Core Test Report
ARINC 818 IP CORE Hardware
Configuration Index (CID)
ARINC 818 IP CORE Requirement
Traceability Report
ARINC 818 IP CORE Problem
Report Records
ARINC 818 IP CORE Configuration
Management Records
ARINC 818 IP CORE Process
Assurance Audit Reports (6 reports)
ARINC 818 IP CORE
Accomplishments Summary
Firmware reference design for
representative hardware
ARINC 818 IP CORE VHDL Test
benches
GRT ISO 9001 Product Realization
(QMS 700)
GRT QMS product realization records
(QMS-710-R, QMS-732-R,
ARINC 818 IP Core User's Manual
Yes
Yes
3
6.1.1(1,2); 6.2.1(1)
Yes
Yes
Yes
Yes
3
4
6.1.1(1,2); 6.2.1(1)
5.3.1(1); 5.4.1(2);
5.5.1(1)
Yes
Yes
2,3
6.1.1(1); 6.2.1(1,2)
Yes
No
2,3, 4
Yes
No
2,3
5.1.1(3); 5.2.1(3);5.3.1(3); 5.4.1(4);
5.5.1(4); 6.1.1(3); 6.2.1(4); 7.1(3)
5.5.1(1); 7.1(1,2,3)
Yes
No
2,3
7.1(2); 8.1(1,2,3)
Yes
Yes
4
Yes
No
na
na
Yes
Yes
na
na
Yes
Yes
na
na
Yes
No
na
na
Yes
Yes
na
na
*Certification authorities will have access to source code if needed.
3 Licensing
GRT uses the SignOnce Agreement and licenses the core on a per project basis. A project is
defined as a certified piece or suite of equipment. This equipment may have multiple instances of
the core instantiated.
The IP Core licensing includes two components:
1) An "R&D Use" license that is purchased at the beginning of a program
2) A Resale (production) license that is purchased when the project begins series production.
The ARINC 818 Development Packages includes the "R&D Use" license.
The production license is purchased separately.
4 ARINC 818 Design & Development Tools
4.1
Video and Protocol Analyzer
GRT offers an ARINC 818 Video and Protocol Analyzer
(VPA). The VPA captures and decodes ARINC 818 video
data, showing not only byte by byte details, but also
verifying all aspects of the protocol. In addition, video line
and frame timing is calculated. A customizable profile
allows users to set-up normal and out of range conditions
for all key parameters. The ARINC 818 VPA is invaluable
in debugging and verifying ARINC 818 transmitter
4
ARINC 818 Video and Protocol Analyzer GUI
implementations. VPAs are configured for a single link speed, such as 1.062 or 3.187Gbps.
You can read more about the analyzer at the following link:
http://www.greatrivertech.com/docs/datasheets/ARINC_818_Analyzer.pdf
4.2
ARINC 818 Video Source & Frame Grabbers
Great River Technology offers ARINC 818 video sources and frame grabbers in a number of form
factors (PCI, PMC, PCIe, XMC) and with different capabilities. Since ARINC 818 projects are built
around a customer specific ICD, GRT can customize any of our development tools to match a
customer’s ICD.
4.2.1 Gravity Series Frame Grabbers and Graphics Generators
Gravity series cards are built on the PCI bus and are suitable for operation
for ARINC 818 video streams up to 3.1875Gbps. The bus throughput is
100-160MB/s depending on the system.
Examples
GRAV64_PCI_FCAV_FO850_2125 – Receive or transmit ARINC 818,
display on a VGA port
GRAV64_PMC_FCAV_FO850_2125_DVI_Rx – Receive or transmit
ARINC 818, convert DVI to ARINC 818.
GRAVity PMC Card
4.2.2 Matrix Series Frame Grabbers and Graphics Generators
Matrix series cards are built on the PCIe four lane bus and are suitable
for ARINC 818 video streams up to 4.25Gbps. The throughput of the
matrix cards are 500MB/s +.
Examples:
MTRX_PCIe4_FCAV_FO850_31875_DVI_Rx – Receive or transmit
ARINC 818, convert DVI to ARINC 818, display on VGA.
MTRX_XMC4_FCAV_FO850_31875_DVI_Tx – Receive or transmit
ARINC 818, display on DVI
Matrix PCIe4 Card
4.2.3 Stand Alone Module (SAMs) Format Converter
GRT’s SAMs are an easy way to convert from ARINC 818 to DVI or
DVI to ARINC 818. SAMs are customized based on customer ICDs.
SAMs are also available with a USB interface to adjust header
parameters.
Examples:
GRAV_SAM_DVI2F_FO850_1062_SXGA+_M
converter for SXGA+ mono.
- DVI to ARINC 818
ARINC 818 Stand Alone Module
5
5 Development Packages
GRT has bundled together ARINC 818 IP cores with essential development tools at a discounted
price. These development packages are configured for engineers developing Rx, Tx or Rx/Tx
implementations.
5.1
ARINC 818 Receiver Development Package
This is for engineers developing an ARINC 818 receiver on a Xilinx or Altera development
board.
1. Rx Only Core with R&D License
2. Gravity, Matrix or SAM Video Source & Test Pattern Generator
3. Reference Design for Certain Xilinx or Altera development boards (customer supplies
board)
4. Email and Phone engineering support for design integration
5.2
ARINC 818 Transmitter Development Package
This is for engineers developing an ARINC 818 transmitter on a Xilinx or Altera development
board.
1. Tx Only Core with R&D License
2. Video and Protocol Analyzer (VPA)
3. Reference Design for Certain Xilinx or Altera development boards (customer supplies
board)
4. Email and Phone engineering support for design integration
5.3
ARINC 818 Total Development Environment Package
This is for engineers developing an ARINC 818 transmitter and receiver on a Xilinx or Altera
development board.
1. Rx/Tx; Rx Only; Tx Only and Dual Transceiver with R&D License
2. Video and Protocol Analyzer (VPA)
3. Gravity, Matrix or SAM Video Source & Test Pattern Generator
4. Reference Design for Certain Xilinx or Altera development boards (customer supplies
board)
5. Email and Phone engineering support for design integration
6