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User Manual
ETE/ETX Module
MSC ETE-PV510
Intel® AtomTM D510 Dual Core
Rev. 1.8
2014-09-19
ETE-PV510
Rev. 1.8
User Manual
Preface
Copyright Notice
Copyright © 2014 MSC Technologies GmbH. All rights reserved.
Copying of this document, and giving it to others and the use or communication of the
contents thereof, is forbidden without express authority. Offenders are liable to the payment
of damages.
All rights are reserved in the event of the grant of a patent or the registration of a utility model
or design.
Important Information
This documentation is intended for qualified audience only. The product described herein is
not an end user product. It was developed and manufactured for further processing by
trained personnel.
Disclaimer
Although this document has been generated with the utmost care no warranty or liability for
correctness or suitability for any particular purpose is implied. The information in this
document is provided “as is” and is subject to change without notice.
EMC Rules
This unit has to be installed in a shielded housing. If not installed in a properly shielded
enclosure, and used in accordance with the instruction manual, this product may cause radio
interference in which case the user may be required to take adequate measures at his or her
owns expense.
Trademarks
All used product names, logos or trademarks are property of their respective owners.
Certification
MSC Technologies GmbH is certified according to DIN EN ISO 9001:2000 standards.
Life-Cycle-Management
MSC products are developed and manufactured according to high quality standards. Our lifecycle-management assures long term availability through permanent product maintenance.
Technically necessary changes and improvements are introduced if applicable. A productchange-notification and end-of-life management process assures early information of our
customers.
Product Support
MSC engineers and technicians are committed to provide support to our customers
whenever needed.
Before contacting Technical Support of MSC Technologies GmbH, please consult the
respective pages on our web site at www.msc-technologies.eu for the latest documentation,
drivers and software downloads.
If the information provided there does not solve your problem, please contact our Technical
Support:
Email: support@msc-technologies.eu
Phone: +49 8165 906-200
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ETE-PV510
Rev. 1.8
User Manual
Content
Content ....................................................................................................................................... 3
1 General Information ................................................................................................................. 5
1.1
Revision History ................................................................................................................... 5
1.2
Introduction .......................................................................................................................... 5
2 Technical Information .............................................................................................................. 6
2.1
Specifications....................................................................................................................... 6
2.2
Block Diagram ..................................................................................................................... 8
2.3
Installation ........................................................................................................................... 9
2.3.1
Jumpers and switches ................................................................................................... 9
2.3.2
Installing a DDR2 SO-DIMM module ............................................................................. 9
2.3.3
Optional NAND Flash .................................................................................................... 9
2.4
Watchdog ............................................................................................................................ 9
2.5
Interrupts, DMA channels, Upper memory ...........................................................................10
2.5.1
PCI Devices .................................................................................................................10
2.5.2
DMA channels..............................................................................................................11
2.5.3
Memory map ................................................................................................................11
2.5.4
SM Bus address map ...................................................................................................11
2.6
Typical power consumption .................................................................................................12
3 Mechanical Specification ........................................................................................................13
3.1
Top view .............................................................................................................................13
3.2
Bottom view ........................................................................................................................13
3.3
Mechanical drawing ............................................................................................................14
3.3.1
Heat spreader / Heatsink options..................................................................................14
4 ETX Connectors .....................................................................................................................15
4.1
Connector X1 (PCI, USB, Audio) .........................................................................................15
4.2
Connector X2 (ISA) .............................................................................................................17
4.3
Connector X3 (CRT, Display, TV out, Serial, Parallel, Mouse, Keyboard)............................19
4.4
Connector X3 - alternate pin out ..........................................................................................23
4.5
Connector X4 (EIDE, Ethernet, Speaker, Battery, I2C, SM Bus, etc.) ..................................24
4.6
Connector X5 (FAN)............................................................................................................26
4.7
Connectors X7, X8 (SATA)..................................................................................................26
4.8
Connectors X10, X11 (Mini USB) ........................................................................................27
4.9
Interrupt Routing on PCI Devices ........................................................................................28
5 BIOS ......................................................................................................................................29
5.1
Introduction .........................................................................................................................29
5.1.1
Startup Screen Overview..............................................................................................29
5.1.2
Activity Detection Background ......................................................................................29
5.2
TrustedCore Setup Utility ....................................................................................................30
5.2.1
Configuring the System BIOS .......................................................................................30
5.2.2
The Main Menu ............................................................................................................32
5.2.2.1 Board Information .....................................................................................................33
5.2.2.2 Drive Settings ...........................................................................................................34
5.2.2.3 Keyboard Features ...................................................................................................35
5.2.2.4 Boot Features ...........................................................................................................36
5.2.3
The Advanced Menu ....................................................................................................36
5.2.3.1 Cache Memory .........................................................................................................37
5.2.3.2 CPU Control Sub-Menu ............................................................................................37
Note : Some options can be different dependent on used type of CPU ....................................37
5.2.3.3 Video (Intel IGD) Control Sub-Menu..........................................................................38
5.2.3.4 ICH Control Sub Menu..............................................................................................39
5.2.3.5 PNP Configuration ....................................................................................................41
5.2.3.6 PCI/PNP ISA IRQ Resource Exclusion Sub-Menu ....................................................42
5.2.3.7 ACPI Control Sub-Menu ...........................................................................................42
5.2.3.8 Integrated Device Control Sub-Menu ........................................................................43
5.2.3.9 I/O Device Configuration Menu .................................................................................44
5.2.3.10 Clock Control Sub-Menu .......................................................................................45
5.2.3.11 Watchdog Options.................................................................................................46
5.2.4
The Security Menu .......................................................................................................47
5.2.5
The Power Menu ..........................................................................................................48
5.2.5.1 Hardware Monitor .....................................................................................................48
5.2.6
The Boot Menu ............................................................................................................49
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5.2.7
The Exit Menu ..............................................................................................................50
5.3
Bios Update ........................................................................................................................51
5.4
Bios Crisis Recovery ...........................................................................................................51
5.4.1
Blind Reset to defaults .................................................................................................51
5.4.2
Crisis Recovery / Clear backup EEPROM Jumper ........................................................52
5.4.3
Crisis Recovery software ..............................................................................................53
5.5
Diagnostics Postcodes ........................................................................................................55
5.5.1
Bootblock Bios Postcodes ............................................................................................55
5.5.2
System Bios Postcodes ................................................................................................55
5.5.3
Memory Detection Postcodes .......................................................................................59
5.5.4
ACPI Postcodes ...........................................................................................................59
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ETE-PV510
Rev. 1.8
User Manual
1 General Information
1.1
1.2
Revision History
Rev.
Date
Description
1.0
22.09.2010
first release
1.1
14.01.2011
IRQ table correction
1.2
1.3
1.4
1.5
1.6
1,7
1.8
21.02.2011
28.02.2011
11.03.2011
26.07.2011
28.11.2011
11.10.2013
2014-09-19
Bios Features added
Added Temperature Zones in HW Monitoring Chapter
Minor corrections
Minor corrections
Minor corrections
Added supported SIO, changed contact information
New covering page
Introduction
The ETe-PV510 is an all-in-one AtomTM CPU module. It is fully compliant with the ETX
3.0 standard.
The module is based on Intel AtomTM CPUs N450, D410 and D510 with the Intel I/O
Controller Hub 8 Mobile (ICH8M).
These Intel AtomTM CPUs are on the Intel embedded roadmap, which means that the
processors are available long term.
The ETE- PV510 supports DDR2 memory modules. It provides a 200-pin SO-DIMM
socket providing the flexibility to configure the system up to 2GB of DDR2-DRAM.
The integrated graphics controller contains a refresh of the 3 rd generation graphics core.
An analog RGB and a single LVDS channel are supported by this GPU.
On board features include a 10/100Base-T Ethernet controller, two EIDE ports, audio,
parallel / floppy, serial, keyboard and mouse interfaces, six USB2.0 ports and two SATA
ports.
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ETE-PV510
Rev. 1.8
User Manual
2 Technical Information
2.1
Specifications
Core
CPU
Intel® Atom TM Processor soldered.
D510, 1.66GHz, dual core, 400MHz GPU, DMI
D410, 1.66GHz, single core, 400MHz GPU, DMI
N450, 1.66GHz, single core, 200MHz GPU, DMI
Chip Set
Intel ® 82801HEM (ICH8M-E)
L2 Cache
512KB (N450 and D410) or 1MB (D510)
Memory
200-Pin SO-DIMM socket for DDR2 (max. 2GByte)
ISA-Bus Interface
PCI to ISA Bridge ITE8888 (ETX connector X2)
Note: Chipset does not support ISA-DMA
PCI-Bus Interface
Intel ® 82801 ICH8 M (ETX connector X1)
Video
Integrated Graphics Engine
CRT-Interface
Flat Panel Interface (LVDS 18bit single channel)
Intel ® Dynamic Video Memory Technology 4.0
DirectX® 9 compliant Pixel Shader 2.0
MPEG2 Hardware Acceleration
Ethernet
Realtek RTL8103T (10/100Base-T)
Notes on using WinCE driver :
This product is covered by one or more of the following patents:
US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776,
and US6,327,625
Audio
HDA codec VIA® VT1708S
USB
integrated in Intel ® 82801HEM ICH8 M:
6 USB 1.1/2.0 ports
EIDE (PIDE)
integrated in Intel ® 82801HEM ICH8 M:
1 Port for up to 2 devices
Ultra ATA/66/100
(optional NAND SSD, see chapter 2.3.3)
EIDE (SIDE)
JMICRON® JMB368 PCIe to PATA controller:
1 Port for up to 2 devices
Ultra ATA/66/100
(OPROM enable / disable via SETUP)
Floppy Disk
integrated in W83627 SIO (pins shared with parallel port)
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Rev. 1.8
User Manual
SATA
integrated in Intel ® 82801HEM ICH8 M:
2 Ports
Serial, COM1, COM2
integrated in W83627 SIO:
2 x TTL
IrDA on COM2
Note : only Winbond 83627HG ( Device ID 0x52 is
supported )
Parallel
integrated in W83627 SIO:
1 Parallel Port (PS/2-compatible/ECP/EPP via
SETUP configurable, pins shared with floppy port)
Keyboard, Mouse
integrated in W83627 SIO:
MFII-Keyboard Interface, PS/2-Mouse Interface
Real time Clock
integrated in 82801HEM ICH8 M (external battery
required)
Watchdog
Microcontroller PIC12F509A:
Start delay and timeout configurable via SETUP
generates hardware reset
TPM (on request)
Trusted Platform Module TPM 1.2:
SLB 9635 TT 1.2
EDID-EEPROM
on Board EDID EEPROM:
enable / disable via SETUP
BIOS
Phoenix BIOS in SPI Flash device
EEPROM
EEPROM for CMOS Setup backup
System Monitoring
EMC2104: 1 fan with Tacho input (valid only if optional fan
connector is used)
3 temperatures (CPU, memory and board)
1 voltage (+5.0V)
W83627 SIO: 6 voltages (Vcore (CPU), +5.0V, +3.3V,
+1.5V, +1.05V, Vbat:)
1
Power supply
+5V ±5%
Typical supply current1
D510: 3.01 A (see chapter 2.6)
D410: 2.72 A (see chapter 2.6)
N450: 2.32 A (see chapter 2.6)
Typical CMOS battery
power consumption
2.7 µA
RTC / CMOS integrated in Intel
Measured with Windows XP at 99% work load.
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82801HEM ICH8 M
ETE-PV510
Environment
Rev. 1.8
User Manual
Temperature
0 ... + 60°C (operating),
-25 ... + 85°C (non operating)
Humidity (rel.)
10 … 90 % non condensing (operating),
5 … 95 % non condensing (non operating)
Note:
A heat spreader plate is available from MSC providing a
standard thermal interface for the module.
The heat spreader is not a heat sink!
Dimensions
2.2
95 x 114 x 12 mm
Block Diagram
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ETE-PV510
2.3
Rev. 1.8
User Manual
Installation
2.3.1 Jumpers and switches
The description of the Crisis Recovery Jumper (also Clear backup EEPROM Jumper)
can be found in chapter 5.4.2.
2.3.2 Installing a DDR2 SO-DIMM module
The ETE-PV510 board has a standard 200-pin SO-DIMM socket for 1.8V DDR2-SDRAM
SO-DIMM modules. The chipset supports 256-Mbit, 512-Mbit and 1-Gbit technologies
providing maximum capacity of 2GB.
Note:
SO-DIMM Module height should not exceed 1260 mil (= 32 mm)
2.3.3 Optional NAND Flash
An on module NAND Flash (1GB, 2GB or 4GB) can be assembled connected to the
primary IDE.
A second IDE device on the primary IDE cannot be used together with the flash.
The on module flash is configured as a master device.
2.4
Watchdog
The ETE- PV510 board has a watchdog function implemented in a PIC Microcontroller.
The watchdog can be enabled and configured in the BIOS Setup.
If the watchdog is enabled a counter is started which generates a reset if it is not
retriggered within a programmable time window.
Possible watchdog delays: 1s, 5s, 10s, 30s, 1min, 5min, 10min, 30min
Possible watchdog timeout: 0.4s, 1s, 5s, 10s, 30s, 1min, 5min, 10min
The time delay starts as soon as it is enabled in the BIOS
MSC provides a software API which gives the application software access to the
Watchdog functionality if needed.
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ETE-PV510
2.5
Rev. 1.8
User Manual
Interrupts, DMA channels, Upper memory
IRQ
used for
available
comment
0
Timer 0
No
1
Keyboard
No
2
Slave 8259
No
3
COM1 / COM2
Yes
(1)
4
COM2 / COM1
Yes
(1)
5
LPT1
Yes
(1)/(2)
6
Floppy Disk Controller
Yes
(1)
7
LPT1
Yes
(1)/(2)
8
Real Time Clock
No
9
ACPI
No
10
COM3 / COM4
Yes
(1)/(2)
11
COM4 / COM3
Yes
(1)/(2)
12
PS/2 Mouse
Yes
(1)
13
Floating Point Unit
No
14
Primary IDE
No
15
PCI / ISA
Yes
(1) Only available if the device is disabled in setup
(2) Can be used by external Super I/O controller FDC37C669
2.5.1 PCI Devices
PCI Device
PCI Interrupt
REQ/GNT (0..5)
IDSEL
PCI to ISA ITE8888
serial
4/45/5
AD29
Slot 0
INT A
0/0
AD19
Slot 1
INT B
1/1
AD20
Slot 2
INT C
2/2
AD21
Slot 3
INT D
3/3
AD22
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User Manual
2.5.2 DMA channels
DMA
used for
available
0
comment
Yes
1
(ECP, if enabled)
(No)
2
Floppy Disk Controller
No
3
(ECP, if enabled)
(No)
4
Cascade
No
5..7
---
Yes
LPT ECP mode, if enabled
LPT ECP mode (default)
2.5.3 Memory map
Upper Memory
used for
available
comment
C0000h. CFFF0h.
VGA BIOS
No
64 KB VGA BIOS
Yes
ISA bus or shadow RAM
D0000h. DFFF0h.
E3C70h. E3FF0h.
System BIOS
No
E4000h. FFFF0h.
System BIOS
No
2.5.4 SM Bus address map
Device
A6 A5 A4 A3 A2 A1
A0
R/W
address *)
SM Bus host
0
0
0
1
0
0
0
x
10h / 08h
clock synthesizer IC9LPRS365
1
1
0
1
0
0
1
x
D2h / 69h
HW monitor EMC2104
0
1
0
1
1
1
1
x
5Eh / 2Fh
SIO W83627HF (default)
0
0
1
0
1
1
0
x
5Ah / 2Dh
SIO W83627HF Temp3 default
1
0
0
1
0
0
0
x
90h / 48h
SIO W83627HF Temp2 default
1
0
0
1
0
0
1
x
92h / 49h
CMOS backup EEPROM #1
1
0
1
0
1
0
0
x
A8h / 54h
CMOS backup EEPROM #2
1
0
1
0
1
0
1
x
AAh / 55h
SPD EEPROM (SO-DIMM)
1
0
1
0
0
0
0
x
A0h / 54h
*) 8 bit address (with R/W) / 7 bit address (without R/W)
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ETE-PV510
2.6
Rev. 1.8
User Manual
Typical power consumption
D510
Mode:
Voltage: Current: Power: Description:
DOS
4.99 V
2.43 A
12.1 W
Dos Prompt
Win XP 1%
4.99 V
2.26 A
11.3 W
Idle mode
Win XP 99% 4.99V
3.01 A
15.0 W
99% work load
D410
Mode:
Voltage: Current: Power: Description:
DOS
4.99 V
2.52 A
12.6 W
Dos Prompt
Win XP 1%
4.99 V
2.38 A
11.9 W
Idle mode
Win XP 99% 4.99V
2.72 A
13.6 W
99% work load
N450
Mode:
Voltage: Current: Power: Description:
DOS
5.00 V
2.22 A
11.1 W
Dos Prompt
Win XP 1%
5.00 V
2.12 A
10.2 W
Idle mode
Win XP 99% 5.00V
2.32 A
11.6W
99% work load
(Measurement includes power consumption of ca. 1.5 W from carrier board, keyboard,
mouse, boot device etc.)
12 / 59
ETE-PV510
Rev. 1.8
3
Mechanical Specification
3.1
Top view
User Manual
X10 X11
X8
X4
X2
X7
X3
X1
PIN1
X5
3.2
Bottom view
X4
X2
X1
X3
13 / 59
ETE-PV510
3.3
Rev. 1.8
User Manual
Mechanical drawing
2,5mm
X4
X2
X3
X1
1,8
3.3.1 Heat spreader / Heat sink options

Heat spreader with through hole standoffs (2.7mm)

Heat spreader with threaded corner standoffs (2.5mm)

Heat sink with through hole standoffs (2.7mm)

Heat sink with threaded corner standoffs (2.5mm)

Fan kit 60 mm x 60 mm
14 / 59
ETE-PV510
Rev. 1.8
4
ETX Connectors
4.1
Connector X1 (PCI, USB, Audio)
User Manual
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
GND
2
GND
51
VCC
52
VCC
3
PCICLK3
4
PCICLK4
53
PAR
54
SERR#
5
GND
6
GND
55
GPERR#
56
RESERVED
7
PCICLK1
8
PCICLK2
57
PME#
58
USB2#
9
REQ3#
10
GNT3#
59
LOCK#
60
DEVSEL#
11
GNT2#
12
3.3V
61
TRDY#
62
USB3#
13
REQ2#
14
GNT1#
63
IRDY#
64
STOP#
15
REQ1#
16
3.3V
65
FRAME#
66
USB2
17
GNT0#
18
RESERVED
67
GND
68
GND
19
VCC
20
VCC
69
AD16
70
CBE2#
21
SERIRQ
22
REQ0#
71
AD17
72
USB3
23
AD0
24
3.3V
73
AD19
74
AD18
25
AD1
26
AD2
75
AD20
76
USB0#
27
AD4
28
AD3
77
AD22
78
AD21
29
AD6
30
AD5
79
AD23
80
USB1#
31
CBE0#
32
AD7
81
AD24
82
CBE3#
33
AD8
34
AD9
83
VCC
84
VCC
35
GND
36
GND
85
AD25
86
AD26
37
AD10
38
AUXAL
87
AD28
88
USB0
39
AD11
40
MIC
89
AD27
90
AD29
41
AD12
42
AUXAR
91
AD30
92
USB1
43
AD13
44
ASVCC
93
PCIRST#
94
AD31
45
AD14
46
SNDL
95
INTC#
96
INTD#
47
AD15
48
ASGND
97
INTA#
98
INTB#
49
CBE1#
50
SNDR
99
GND
100
GND
15 / 59
ETE-PV510
Signal
VCC
GND
3V
RESERVED
Signal
Rev. 1.8
Description
Power Supply +5V, ± 5%
Power Ground
Power Supply +3.3V
Not connected
Description of PCI Bus Signals
User Manual
I/O
I
I
O
n. a.
Note
external supply
external supply
Do not use externally
Do not connect
I/O
Note
PCI outputs 3,3V signal level
PCI inputs 5V tolerant
PCICLK1..4.
REQ0..3#
GNT0 #
GNT1..3#
AD0..31
CBE0..3#
PAR
SERR#
GPERR#
PME#
LOCK#
DEVSEL#
TRDY#
IRDY#
STOP#
FRAME#
PCIRST#
INTA#
INTB#
INTC#
INTD#
SERIRQ
Signal
USB0, USB0#
USB1, USB1#
USB2, USB2#
USB3, USB3#
USB4, USB4#
USB5, USB5#
Signal
SNDL
SNDR
AUXAL
AUXAR
MIC
ASGND
ASVCC
PCI clock output
PCI bus request
PCI bus grant
PCI bus grant
PCI Address bus / Data bus
PCI bus command/byte enables
PCI bus parity
PCI bus system error
PCI bus grant parity error
PCI bus power management event
PCI bus lock
PCI bus device select
PCI bus target ready
PCI bus initiator ready
PCI bus stop
PCI bus frame
PCI bus reset
PCI bus interrupt A
PCI bus interrupt B
PCI bus interrupt C
PCI bus interrupt D
Serial interrupt request
Description of USB Signals
USB Port 0
USB Port 1
USB Port 2
USB Port 3
USB Port 4
USB Port 5
Description of Audio Signals
Line-Level stereo output left
Line-Level stereo output right
Auxiliary input A left
Auxiliary input A right
Microphone input
Analog ground of sound controller
Analog supply of sound controller
16 / 59
O
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PU 8k2 3,3V
PD 2k2
PU 8k2 3,3V
PU 8k2 3,3V
internal PU 20k 3,3Vsus
PU 8k2 3,3V
PU 8k2 3,3V
PU 8k2 3,3V
PU 8k2 3,3V
PU 8k2 3,3V
PU 8k2 3,3V
3,3V signal level
PU 8k2 3,3V
PU 8k2 3,3V
PU 8k2 3,3V
PU 8k2 3,3V
PU 10k 3,3V
Note
5V tolerant; internal PD 15k
5V tolerant; internal PD 15k
5V tolerant; internal PD 15k
5V tolerant; internal PD 15k
5V tolerant; internal PD 15k
5V tolerant; internal PD 15k
I/O
O
O
I
I
I
I
O
Note
0.7VRMS
0.7VRMS
+5.0V
ETE-PV510
4.2
Rev. 1.8
User Manual
Connector X2 (ISA)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
GND
2
GND
51
VCC
52
VCC
3
SD14
4
SD15
53
SA6
54
IRQ5
5
SD13
6
MASTER#
55
SA7
56
IRQ6
7
SD12
8
DREQ7
57
SA8
58
IRQ7
9
SD11
10
DACK7#
59
SA9
60
SYSCLK
11
SD10
12
DREQ6
61
SA10
62
REFSH#
13
SD9
14
DACK6#
63
SA11
64
DREQ1
15
SD8
16
DREQ5
65
SA12
66
DACK1#
17
MEMW#
18
DACK5#
67
GND
68
GND
19
MEMR#
20
DREQ0
69
SA13
70
DREQ3
21
LA17
22
DACK0#
71
SA14
72
DACK3#
23
LA18
24
IRQ14
73
SA15
74
IOR#
25
LA19
26
IRQ15
75
SA16
76
IOW#
27
LA20
28
IRQ12
77
SA18
78
SA17
29
LA21
30
IRQ11
79
SA19
80
SMEMR#
31
LA22
32
IRQ10
81
IOCHRDY
82
AEN
33
LA23
34
IO16#
83
VCC
84
VCC
35
GND
36
GND
85
SD0
86
SMEMW#
37
SBHE#
38
M16#
87
SD2
88
SD1
39
SA0
40
OSC
89
SD3
90
NOWS#
41
SA1
42
BALE
91
DREQ2
92
SD4
43
SA2
44
TC
93
SD5
94
IRQ9
45
SA3
46
DACK2#
95
SD6
96
SD7
47
SA4
48
IRQ3
97
IOCHK#
98
RSTDRV
49
SA5
50
IRQ4
99
GND
100
GND
17 / 59
ETE-PV510
Signal
VCC
GND
Signal
SD0..15
Rev. 1.8
User Manual
Description
Power Supply +5V, ± 5%
Power Ground
I/O
I
I
Note
external supply
external supply
ISA Bus Signals
ISA Data bus
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note
all ISA outputs 5V signal level
(PU 8k2 5V)
all ISA inputs 5V tolerant
PU 8k2 5V
PU 8k2 5V
internal PU 50k 5V
PD 4k7
PD 4k7
PU 8k2 5V
PU 1k0 5V
I/O
I/O
PU 8k2 5V
PU 1k0 5V
I/O
I/O
I
I/O
I/O
I
I/O
PU 8k2 5V
PU 8k2 5V
PU 4k7 5V
PU 1k0 5V
PU 1k0 5V
PU 1k0 5V
PU 1k0 5V
I
I
O
O
O
I
I/O
I/O
I
I
I/O
I
PU 1k0 5V
PU 1k0 5V
SA0..19
LA17..23
SBHE#
BALE
AEN
MEMR#
SMEMR#
ISA Address bus
ISA Address bus
ISA Byte High Enable
ISA Address Latch Enable
ISA Address Enable
ISA memory read
ISA memory read in lowest
1MB address range
MEMW#
ISA memory write
SMEMW# ISA memory write in lowest
1MB address range
IOR#
ISA IO read
IOW#
ISA IO write
IOCHK#
ISA IO check
IOCHRDY ISA IO channel ready
M16#
ISA 16Bit memory device
IO16#
ISA 16Bit IO device
REFSH# ISA memory refresh cycle
pending
NOWS#
ISA No wait states
MASTER# ISA Master
SYSCLK ISA System clock (8 MHz)
OSC
ISA Oscillator (14,31818 MHz)
RSTDRV ISA Reset signal
DREQ0..7 ISA DMA request
DACK0#..7# ISA DMA acknowledge
TC
ISA DMA end
IRQ3..7
ISA Interrupt request
IRQ9..12 ISA Interrupt request
IRQ14
ISA Interrupt request
IRQ15
ISA Interrupt request
18 / 59
PD 8k2
PD 4k7
IRQ table see 2.5; PU 8k2 5V
IRQ table see 2.5; PU 8k2 5V
IRQ table see 2.5; PU 8k2 5V
IRQ table see 2.5; PU 8k2 5V
ETE-PV510
4.3
Rev. 1.8
User Manual
Connector X3
(CRT, Display, TV out, Serial, Parallel, Mouse, Keyboard)
Standard pin out with LVDS and LPT
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
GND
2
GND
51
LPT/FLPY#
52
RESERVED
3
R
4
B
53
VCC
54
GND
5
HSY
6
G
55
STB#/RES
56
AFD#/DENSEL
7
VSY
8
DDCK
57
RESERVED
58
PD7/RES
9
DETECT#
10
DDDA
59
IRRX
60
ERR#/HDSEL#
11
LCDDO16
12
LCDDO18
61
IRTX
62
PD6/RES
13
LCDDO17
14
LCDDO19
63
RXD2
64
INIT#/DIR#
15
GND
16
GND
65
GND
66
GND
17
LCDDO13
18
LCDDO15
67
RTS2#
68
PD5/RES
19
LCDDO12
20
LCDDO14
69
DTR2#
70
SLIN#/STEP#
21
GND
22
GND
71
DCD2#
72
PD4/
DSKCHG#
23
LCDDO8
24
LCDDO11
73
DSR2#
74
PD3/RDATA#
25
LCDDO9
26
LCDDO10
75
CTS2#
76
PD2/WP#
27
GND
28
GND
77
TXD2
78
PD1/TRK0#
29
LCDDO4
30
LCDDO7
79
RI2#
80
PD0/INDEX#
31
LCDDO5
32
LCDDO6
81
VCC
82
VCC
33
GND
34
GND
83
RXD1
84
ACK/DRV1
35
LCDDO1
36
LCDDO3
85
RTS1#
86
BUSY#/MOT1#
37
LCDDO0
38
LCDDO2
87
DTR1#
88
PE/WDATA#
39
VCC
40
VCC
89
DCD1#
90
SLCT#/
WGATE#
41
JILI_DAT
42
LTGIO0
91
DSR1#
92
MSCLK
43
JILI_CLK
44
BLON#
93
CTS1#
94
MSDAT
45
BIASON
46
DIGON
95
TXD1
96
KBCLK
47
COMP
48
Y
97
RI1#
98
KBDAT
49
SYNC
50
C
99
GND
100
GND
19 / 59
ETE-PV510
Rev. 1.8
Signal
VCC
GND
N.C.
LTGIO0
DETECT#
Signal
HSYNC
VSYNC
R
Description
Power Supply +5VDC, ± 5%
Power Ground
Not connected
General Purpose IO
Not connected
User Manual
I/O
I
I
n. a.
O
n. a.
Note
external supply
external supply
I/O
O
O
O
Note
3V3 signal level
3V3 signal level
GPIO48
DDCK
DDDA
Description of analog CRT signals
Horizontal Sync
Vertical Sync
Red channel RGB Analog Video
Output
Green channel RGB Analog Video
Output
Blue channel RGB Analog Video
Output
Display Data Channel Clock
Display Data Channel Data
Signal
SYNC
Y
C
COMP
Description of TV signals (option)
n. c.
n. c.
n. c.
n. c.
Signal
Description of COM signals
I/O
Data terminal ready of COM1/COM2
Ring indicator of COM1/COM2
Data transmit of COM1/COM2
Data receive of COM1/COM2
Clear to send of COM1/COM2
Request to send of COM1/COM2
Data carrier detect of COM1/COM2
Data set ready of COM1/COM2
O
I
O
I
I
O
I
I
Description of keyboard and
infrared signals
Keyboard Data
Keyboard Clock
Mouse Data
Mouse Clock
Infrared Transmit
Infrared Receive
I/O
Note
I/O
O
I/O
O
O
I
PU 8k2 5V
PU 8k2 5V
PU 8k2 5V
PU 8k2 5V
G
B
DTR1..2#
RI1..2#
TXD1..2
RXD1..2
CTS1..2#
RTS1..2#
DCD1..2#
DSR1..2#
Signal
KBDAT
KBCLK
MSDAT
MSCLK
IRTX
IRRX
20 / 59
O
O
I/O
I/O
PU 2k2 5V
PU 2k2 5V
I/O Note
n. a.
n. a.
n. a.
n. a.
Note
All TTL signal level
PU 470k 5V
PU 470k 5V
PU 470k 5V
PU 470k 5V
PU 470k 5V
ETE-PV510
Rev. 1.8
Signal
LPT/FLPY#
STB#/RES
AFD#/DENSEL
PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/RES
PD6/RES
PD7/RES
ERR#/HDSEL#
INIT#/DIR#
SLIN#/STEP#
ACK/DRV1
BUSY#/MOT1#
PE/WDATA#
SLCT#/WGATE#
Signal
LPT/FLPY#
STB#/RES
AFD#/DENSEL
PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/RES
PD6/RES
PD7/RES
ERR#/HDSEL#
INIT#/DIR#
SLIN#/STEP#
ACK/DRV1
BUSY#/MOT1#
PE/WDATA#
SLCT#/
WGATE#
User Manual
Description of FDC signals
(shared with LPT)
LPT or Floppy Interface
configuration input
n. c.
density select:
low = 250/300Kb/s
high = 500/1000Kb/s
Index signal
Track signal
Write protect signal
Raw data read
Disc changed
n. c.
n. c.
n. c.
Head select
Direction
Motor step
Drive 1 select
Motor 1 select
Raw write data
Write enable
I/O
Description of LPT signals
(shared with FDC)
LPT or Floppy Interface
configuration input
Strobe signal
Automatic feed
Data bus D0
Data bus D1
Data bus D2
Data bus D3
Data bus D4
Data bus D5
Data bus D6
Data bus D7
LPT error
Initiate
Select
Acknowledge
Busy
Paper empty
Power ON
I/O
21 / 59
I
Note
Connect to GND; PU 10k 5V
O
I
I
I
I
I
O
O
O
O
O
O
O
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
I
I
I
I
Note
Connect to VCC (resistor
4K7); PU 10k 5V
ETE-PV510
Signal
BIASON
DIGON
BLON#
LCDDO0
LCDDO1
LCDDO2
LCDDO3
LCDDO4
LCDDO5
LCDDO6
LCDDO7
LCDDO8
LCDDO9
LCDDO10
LCDDO11
LCDDO12
LCDDO13
LCDDO14
LCDDO15
LCDDO16
LCDDO17
LCDDO18
LCDDO19
JILI_DAT
JILI_CLK
Rev. 1.8
Description of LVDS Flat panel
signals
Display contrast voltage
Display Power ON
Display Backlight ON
LVDS_L0LVDS_L0+
LVDS_L1LVDS_L1+
LVDS_L2LVDS_L2+
LVDS_LCLKLVDS_LCLK+
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
n. c.
JILI DATA
JILI CLOCK
22 / 59
User Manual
I/O
O
O
O
O
O
O
O
O
O
O
O
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
n. a.
I/O
I/O
Note
PD 100k
3,3V tolerant
PU 4k7 5V
PU 8k2 3,3V
PU 8k2 3,3V
ETE-PV510
4.4
Rev. 1.8
User Manual
Connector X3 - alternate pin out
LPT
(LPT/FLPY# = high)
Floppy
(LPT/FLPY# = low)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
51
LPT/FLPY#
52
RESERVED
51
LPT/FLPY#
52
RESERVED
53
VCC
54
GND
53
VCC
54
GND
55
STB#
56
AFD#
55
RESERVED
56
DENSEL
57
RESERVED
58
PD7
57
RESERVED
58
RESERVED
59
IRRX
60
ERR#
59
IRRX
60
HDSEL#
61
IRTX
62
PD6
61
IRTX
62
RESERVED
63
RXD2
64
INT#
63
RXD2
64
DIR#
65
GND
66
GND
65
GND
66
GND
67
RTS2#
68
PD5
67
RTS2#
68
RESERVED
69
DTR2#
70
SLIN#
69
DTR2#
70
STEP#
71
DCD2#
72
PD4
71
DCD2#
72
DSKCHG#
73
DSR2#
74
PD3
73
DSR2#
74
RDATA#
75
CTS2#
76
PD2
75
CTS2#
76
WP#
77
TXD2
78
PD1
77
TXD2
78
TRK0#
79
RI2#
80
PD0
79
RI2#
80
INDEX#
81
VCC
82
VCC
81
VCC
82
VCC
83
RXD1
84
ACK
83
RXD1
84
DRV
85
RTS1#
86
BUSY#
85
RTS1#
86
MOT
87
DTR1#
88
PE
87
DTR1#
88
WDATA#
89
DCD1#
90
SLCT#
89
DCD1#
90
WGATE#
91
DSR1#
92
MSCLK
91
DSR1#
92
MSCLK
93
CTS1#
94
MSDAT
93
CTS1#
94
MSDAT
95
TXD1
96
KBCLK
95
TXD1
96
KBCLK
97
RI1#
98
KBDAT
97
RI1#
98
KBDAT
99
GND
100
GND
99
GND
100
GND
23 / 59
ETE-PV510
4.5
Rev. 1.8
User Manual
Connector X4
(EIDE, Ethernet, Speaker, Battery, I2C, SM Bus, etc.)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
GND
2
GND
51
SIDE_IOW#
52
PIDE_IOR#
3
5V_SB
4
PWGIN
53
SIDE_DRQ
54
PIDE_IOW#
5
PS_ON
6
SPEAKER
55
SIDE_D15
56
PIDE_DRQ
7
PWRBTN#
8
BATT
57
SIDE_D0
58
PIDE_D15
9
KBINH
10
LILED
59
SIDE_D14
60
PIDE_D0
11
RSMRST#
12
ACTLED
61
SIDE_D1
62
PIDE_D14
13
ROMKBCS#
14
SPEEDLED
63
SIDE_D13
64
PIDE_D1
15
EXT_PRG
16
I2CLK
65
GND
66
GND
17
VCC
18
VCC
67
SIDE_D2
68
PIDE_D13
19
OVCR#
20
GPCS#
69
SIDE_D12
70
PIDE_D2
21
EXTSMI#
22
I2DAT
71
SIDE_D3
72
PIDE_D12
23
SMBCLK
24
SMBDATA
73
SIDE_D11
74
PIDE_D3
25
SIDE_CS3#
26
SMBALRT#
75
SIDE_D4
76
PIDE_D11
27
SIDE_CS1#
28
DASP_S
77
SIDE_D10
78
PIDE_D4
29
SIDE_A2
30
PIDE_CS3#
79
SIDE_D5
80
PIDE_D10
31
SIDE_A0
32
PIDE_CS1#
81
VCC
82
VCC
33
GND
34
GND
83
SIDE_D9
84
PIDE_D5
35
PDIAG_S
36
PIDE_A2
85
SIDE_D6
86
PIDE_D9
37
SIDE_A1
38
PIDE_A0
87
SIDE_D8
88
PIDE_D6
39
SIDE_INTRQ
40
PIDE_A1
89
GPE2#
90
CBLID_P#
41
BATLOW#
42
GPE1#
91
RXD#
92
PIDE_D8
43
SIDE_AK#
44
PIDE_INTRQ
93
RXD
94
SIDE_D7
45
SIDE_RDY
46
PIDE_AK#
95
TXD#
96
PIDE_D7
47
SIDE_IOR#
48
PIDE_RDY
97
TXD
98
HDRST#
49
VCC
50
VCC
99
GND
100
GND
24 / 59
ETE-PV510
Rev. 1.8
User Manual
Signal
VCC
GND
N.C.
Description
Power Supply +5VDC, ± 5%
Power Ground
Not connected
Signal
PIDE_D0..15
PIDE_A0..2
PIDE_CS1#
PIDE_CS3#
PIDE_DRQ
PIDED_AK#
PIDE_RDY
PIDE_IOR#
PIDE_IOW#
PIDE_INTRQ
CBLID_P#
Description of IDE signals
Primary IDE Data bus
Primary IDE Address bus
Primary IDE chip select channel0
Primary IDE chip select channel1
Primary IDE DMA request
Primary IDE DMA acknowledge
Primary IDE ready
Primary IDE IO read
Primary IDE IO write
Primary IDE interrupt request
Cable ID primary
I/O
I/O
O
O
O
I
O
I
O
O
I
I
Note
D7: Internal PD 5k7 to 28k3
SIDE_D0..15
SIDE_A0..2
SIDE_CS1#
Secondary IDE Data bus
Secondary IDE Address bus
Secondary IDE chip select
channel0
Secondary IDE chip select
channel1
Secondary IDE DMA request
Secondary IDE DMA acknowledge
Secondary IDE ready
Secondary IDE IO read
Secondary IDE IO write
Secondary IDE interrupt request
n. c.
Secondary IDE Master/Slave
negotiation
Hard Drive reset
I/O
O
O
D7: Internal PD31k6
SIDE_CS3#
SIDE_DRQ
SIDED_AK#
SIDE_RDY
SIDE_IOR#
SIDE_IOW#
SIDE_INTRQ
DASP_S
PDIAG_S
HDRST#
Signal
TXD+, TXDRXD+, RXDACTLED
LILED
SPEEDLED
Description of Ethernet signals
Ethernet Twisted Pair transmit
signal pair
Ethernet Twisted Pair receive
signal pair
Ethernet activity LED
Ethernet link LED
Ethernet speed LED, ON for
100Mb/s
25 / 59
I/O Note
I
external supply
I
external supply
n. a.
Internal PD 5k7 to 28k3
PU 4k7 3,3V
PU 8k2 3,3V
PD 10k, PU 5V
O
I
PD 4k7
O
I
PU 4k7 3,3V
O
O
I
PD 8k2
n. a.
I
O
3,3V signal level
I/O
O
Note
I
O
O
O
3,3V (10mA sink)
3,3V (10mA sink)
3,3V (10mA sink)
ETE-PV510
4.6
Rev. 1.8
Signal
SPEAKER
Description of Misc. signals
Speaker output
BATT
PWGIN
I2CLK
I2DAT
SMBCLK
SMBDAT
SMBALRT#
KBINH
5V_SB
PS_ON
PWRBTN#
OVCR#
ROMKBCS#
EXT_PRG#
GPCS#
GPE1#
GPE2#
BATLOW#
EXTSMI#
RSMRST#
Battery supply
Power good input
I2C Bus Clock
I2C Bus Data
SM Bus Clock
SM Bus Data
SM Bus Alert
Keyboard inhibit
Supply of internal suspend circuit
Power Save ON
Power Button
Over current detect for USB
n. c.
n. c.
n. c.
n. c.
Ring Input
Battery low
External SMI
Resume Reset
I/O
O
I
I
I/O
I/O
I/O
I/O
I
I
I
O
I
I
n. a.
n. a.
n. a.
n. a.
I
I
I
I
Note
Internal PD 20k ; 3,3V
signal level
3,3V (3,6V max.)
PU 10k 3,3V
PU 2k2 3,3V
PU 2k2 3,3V
PU 6k8 5V
PU 6k8 5V
PU 10k 3,3V_SUS
PU 10k 5V
PU 4k7 5V_SB
Internal PU 20k 3,3V_SUS
PU 8k2 3,3V_SUS
PU 10k 3,3V_SUS
PU 10k 3,3V_SUS
(PU 10k 3,3V_SUS)
3,3V signal level
Connector X5 (FAN)
Pin
Signal
1
GND
2
PWM controlled VCC 5V
3
Fan speed
Connector:
4.7
User Manual
JST S3B-ZR-SM4A-TF
Connectors X7, X8 (SATA)
Pin
Signal X7
Pin
Signal X8
1
GND
1
GND
2
S1_TX+
2
S2_TX+
3
S1_TX-
3
S2_TX-
4
GND
4
GND
5
S1_RX-
5
S2_RX-
6
S1_RX+
6
S2_RX+
7
GND
7
GND
26 / 59
ETE-PV510
4.8
Rev. 1.8
User Manual
Connectors X10, X11 (Mini USB)
Pin
Signal X10
Pin
Signal X11
1
5V
1
5V
2
USB4_Data-
2
USB5_Data -
3
USB4_Data +
3
USB5_Data +
4
USB_ID4
4
USB_ID5
5
GND
5
GND
27 / 59
ETE-PV510
User Manual
Interrupt Routing on PCI Devices
0
PCI Express
Root Port
Device 28
Function 0/1
0
USB UHCI
Host
Controller
Device 29
Function 0
USB UHCI
Host
Controller
Device 29
Function 1
USB UHCI
Host
Controller
Device 29
Function 2
USB EHCI
Controller
Device 29
Function 7
0
ICH PATA
Device 31
Function 1
0
Secondary
IDE
Device 0
Function 0
5
SATA
Device 31
Function 2
0
SMBUS
Device 31
Function 3
0
LAN
Controller
Device 0
Function 0
7
PCI Slot 1
AD19
-
A
B
C
D
PCI Slot 2
AD20
-
D
A
B
C
PCI Slot 3
AD21
-
C
D
A
B
PCI Slot 4
AD22
-
B
C
D
A
PIRQ 7
(INT H)
Device 27
Function 2
PIRQ 6
(INT G)
HD Audio
PIRQ 3
(INT D)
Device 02h
PIRQ 2
(INT C)
Internal
Graphic
Device
PIRQ 1
(INT B)
IDSEL #
or
Device #
PIRQ 0
(INT A)
Slot Number
(or Onboard
Device)
PIRQ 5
(INT F)
Interrupts of Controller
PIRQ 4
(INT E)
Controller
Bus #
4.9
Rev. 1.8
0
A
A
A
B
0
A
0
B
0
C
A
A
A
B
C
A
28 / 59
ETE-PV510
Rev. 1.8
User Manual
5 BIOS
5.1
Introduction
This guide describes the Phoenix TrustedCore Startup screen and contains information
on how to access Phoenix TrustedCore setup to modify the settings which control
Phoenix pre-OS (operating system) functions.
5.1.1 Startup Screen Overview
The Phoenix TrustedCore Startup screen is a graphical user interface (GUI) that is
included in Phoenix TrustedCore products. The default bios behavior is to show an
informational text screen during bios POST phase, but the graphical boot screen can be
enabled in the bios setup. The standard boot screen is a black screen, including a
progress bar at the bottom of the screen. This bar indicates the progress of the Startup
Screen functions and provides user prompting and POST status. The following figure
shows the various parts of a generic Startup Screen at 1024x768 resolution:
5.1.2 Activity Detection Background
While the TrustedCore Startup screen is displayed, press the Setup Entry key (F2 –
TrustedCore default). The TrustedCore Startup Status Bar acknowledges the input, and
at the end of POST, the screen clears and setup launches.
An example of the Startup Status Bar displaying changing state is shown in the following
figure. The “Please Wait…” text is displayed after the F2 key is pressed to acknowledge
user input.
Active status bar:
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5.2
Rev. 1.8
User Manual
TrustedCore Setup Utility
With the Phoenix TrustedCore Setup program, you can modify TrustedCore settings and
control the special features of your computer. The Setup program uses a number of
menus for making changes and turning the special features on or off. This chapter
provides an overview of the Setup utility and describes at a high-level how to use it.
5.2.1 Configuring the System BIOS
To start the Phoenix TrustedCore Setup utility, press [F2] to launch Setup. The Setup
main menu appears.
The BIOS Menu Structure
The BIOS Menu is structured in the following way:
Main
Board Information
Legacy Diskette A:
IDE Primary Master
IDE Primary Slave
SATA Port 0
SATA Port 1
Boot Features
Keyboard Features
Advanced
Cache Sub-Menu
CPU Control Sub-Menu
Video (Intel IGD) Control Sub-Menu
ICH Control Sub-Menu
PnP Configuration
PCI/PNP ISA UMB Region Exclusion
PCI/PNP ISA IRQ Resource Exclusion
ACPI Control Sub-Menu
Integrated Device Sub-Menu
I/O Device Configuration
Clock Control Sub-Menu
Watchdog Options
Security
Power
Hardware Monitor
Boot
Exit
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The Menu Bar
The Menu Bar at the top of the window lists these options:
Menu Items
Description
Main
Use this menu for basic system configuration.
Advanced
Use this menu to set the Advanced Features available on the
system’s chipset.
Security
Use this menu to set User and Supervisor Passwords and
configure TPM.
Power
Use this menu to configure Power-Management features.
Boot
Use this menu to set the boot order in which the BIOS attempts to
boot to OS.
Exit
Exits the current menu.
Use the left and right arrow keys on your keyboard to make a menu selection.
The Legend Bar
Use the keys listed in the legend bar on the bottom of the screen to make your
selections, or to exit the current menu. The following table describes the legend keys and
their alternates:
Key
Function
F1 or Alt-H
General Help window.
Esc
Exit this menu.
Arrow keys left and right
Select a different menu.
Up and down arrow keys
Move cursor up and down.
Tab or Shift-Tab
Move cursor left and right (i.e. at System Time / System Date).
Home or End
Move cursor to top or bottom of window.
PgUp or PgDn
Move cursor to next or previous page.
F5 or -
Select the previous value for the field.
F6 or + or Space
Select the next value for the field.
F9
Load the Default Configuration values (for all menus).
F10
Save and exit.
Enter
Execute command or select Sub-Menu.
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Select an item
To select an item, use the arrow keys to move the cursor to the field you want. Then use
the plus-and-minus value keys to select a value for that field. The Save Values command
in the Exit Menu saves the values currently displayed in all the menus.
Display a Sub-Menu
To display a Sub-Menu, use the arrow keys to move the cursor to the desired sub menu.
Then press Enter.
5.2.2 The Main Menu
The following selections can be made in the Main Menu.. Use the sub menus for further
options.
Feature
Options
Description
Board Information
Sub-Menu
Displays BIOS Version
System Time
Enter Time (HH:MM:SS)
Set the System Time.
System Date
Enter Date (DD/MM/YYYY)
Set the System Date.
Legacy Diskette A
Enabled, Disabled
Selects floppy type.
IDE Primary Master
Sub-Menu Drive Settings
Configure IDE Primary Master
IDE Primary Slave
Sub-Menu Drive Settings
Configure IDE Primary Slave
SATA Port 1
Sub-Menu Drive Settings
Configure SATA Port 1
SATA Port 2
Sub-Menu Drive Settings
Configure SATA Port 2
Boot Features
Sub-Menu
Configure Boot Features
Keyboard Features
Sub-Menu
Configure Keyboard Features
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5.2.2.1 Board Information
Feature
Options
Description
Bios Version
Informative
Shows current bios version.
HW Platform
Informative
Name of the hardware platform
HW Revision
Informative
Hardware revision number
Serial #
Informative
Hardware Serial Number
MAC Address
Informative
Shows MAC Address
Boot Counter
Informative
The number of times this board has
booted up.
CPU String
Informative
CPU Identification string
CPU Speed
Informative
CPU Speed
CPU Class
Informative
CPU ID Class code
CPU Model
Informative
CPU ID Model code
CPU Stepping
Informative
CPU ID Stepping
CPU Cores
Informative
Number of CPU cores
Microcode Patch ID
Informative
CPU Microcode ID
Installed Memory
Informative
Shows installed Memory
Used by Devices
Informative
Shows Memory used by Devices
System Memory
Informative
Amount of memory below 1MB
Extended Memory
Informative
Total amount of memory
UUID
Informative
Shows UUID of module
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5.2.2.2 Drive Settings
The drive settings on the Main Menu control the following device types:
• Hard-disk drives (IDE and SATA)
• Removable-disk drives
• CD-ROM drives
There is one IDE connector on the motherboard, usually labeled "Primary IDE". There
are usually two connectors on each ribbon cable attached to IDE connector. When you
have connected two drives to this connector, the one on the end of the cable is the
Master.
Note: A second IDE device on the primary IDE cannot be used together with the
flash.
The on-module flash is configured as a master device.
When entering Setup, the Main Menu displays the results of Autotyping information
each drive provides its own size and other characteristics–and whether it is configured
as a Master or Slave on the system.
Note: Do not attempt to change these settings unless you have an installed drive that
does not autotype properly (such as an older hard-disk drive that does not support
autotyping).
If you need to change the drive settings, select one of the Master or Slave drives on the
Main Menu. This will display a menu like this:
Note: The capacity is displayed in ‘real’ Mbytes (1MB=1024*1024 Bytes) Drives with a
total capacity greater than 8Gbyte operate in LBA format only.
Feature
Options
Description
Type
None,
ATAPI Removable,
CD-ROM,
IDE Removable,
Other ATAPI,
User,
Auto
None = Autotyping is not able to
supply the drive type or end user has
selected None, disabling any drive that
may be installed.
Auto = Autotyping, the drive itself
supplies the information.
User = You supply the hard-disk drive
information in the following fields.
ATAPI Removable = Removable Disk
Drive
Other ATAPI = non-specific ATAPI
Device
CD-ROM = CD-ROM drive.
Cylinders
1 to 65536 ( only informative )
Number of Cylinders
Heads
1 to 16 ( only informative )
Number of read/write heads
Sectors
1 to 63 ( only informative )
Number of sectors per track
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Feature
Options
User Manual
Description
Multi-Sector Transfers
Disabled, 2 sectors,
4 sectors, 8 sectors,
16 sectors
Any selection except Disabled
determines the number of sectors
transferred per block.
LBA Mode Control
Disabled, Enabled
Enabling LBA causes Logical Block
Addressing to be used in place of
Cylinders, Heads, & Sectors.
32 Bit I/O
Disabled, Enabled
Enables 32-bit communication
between CPU and IDE card. Requires
PCI or local bus.
Transfer Mode
Standard
Fast PIO 1
Fast PIO 2
Fast PIO 3
Fast PIO 4
FPIO 3 / DMA 1
FPIO 4 / DMA 2
Selects the method for transferring the
data between the hard disk and
system memory.
The Setup menu only lists those
options supported by the drive and
platform.
Ultra DMA Mode
Disabled
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Ultra DMA Mode supports 33/66/100
MB/sec transfer rate for fixed disk
drives.
SMART Monitoring
Disabled, Enabled
Displays the status of SMART
Monitoring if supported by the used
drive.
WARNING: Incorrect settings can cause your system to malfunction.
5.2.2.3 Keyboard Features
Feature
Options
Description
NumLock
Auto, On, Off
Selects Power-on state for
NumLock
Key Click
Disabled, Enabled
Enables or disables key click
feature
Keyboard auto-repeat
rate
30/sec, 26.7/sec, 21.8/sec, Selects key repeat rate
18.5/sec, 13.3/sec, 10/sec,
6/sec, 2/sec
Keyboard auto-repeat
delay
¼ sec, ½ sec, ¾ sec, 1
sec
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Selects delay before key repeat
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User Manual
5.2.2.4 Boot Features
Feature
Options
Description
Summary screen
Disabled, Enabled
Enabled displays system configuration
on boot.
Boot-time Diagnostic
Screen
Disabled, Enabled
Enabled displays the diagnostic
screen during boot.
Disabled displays the Boot Logo.
Quick Boot Mode
Disabled, Enabled
Allows the System to skip certain tests
while booting. This will decrease the
time needed to boot the system.
Post Errors
Disabled, Enabled
Pauses and displays Setup Entry or
resume boot prompt if error occurs on
boot. If disabled, system always
attempts to boot.
Extended Memory Testing Normal, Just zero it, None
Determines which type of test will be
performed on extended memory during
POST (above 1 MB).
5.2.3 The Advanced Menu
Feature
Installed O/S
Options
Description
Other,
Win95,
Win98,
WinMe,
Win2000,
WinXP
Select the operating system installed
on your system which you will use
most commonly.
Reset configuration Data
No, Yes
Select ‘Yes’ if you want to clear the
Extended System Configuration Data
(ESCD) area.
Large Disk Access Mode
Other, DOS
Select Other for UNIX, Novell
NetWare. Select DOS for all other
operating systems.
Small Disk Access Mode
No, Yes
Select if CHS translation should be
made for a LBA-capable harddisk with
less than 1024 cylinders, e.g.
CompactFlash(R). If you have
problems with booting from a
CompactFlash(R), try to change this
setting.
NOTE: An incorrect setting can cause
some operating systems to display
unexpected behavior.
No = translate CHS only if HDD has
>1024 cyls.
Yes = translate CHS for all LBAcapable disks.
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Feature
Options
User Manual
Description
Legacy USB Support
Enabled, Disbaled
Enable support for Legacy Universal
Serial Bus
Cache Memory
Sub-Menu
Configures Cache Memory
CPU Control Sub-Menu
Sub-Menu
Configure CPU Control
Video (Intel IGD) Control
Sub-Menu
Sub-Menu
Configure Video (Intel IGD) Control
ICH Control Sub-Menu
Sub-Menu
Configure ICH Control
ACPI Control Sub-Menu
Sub-Menu
Configure ACPI Control
Integrated Device Control
Sub-Menu
Sub-Menu
Configure Integrated Device Control
I/O Device Configuration
Sub-Menu
Configure I/O Device
Clock Control Sub-Menu
Sub-Menu
Configure Clock Control
Watchdog Options
Sub-Menu
Configure Watchdog Options
5.2.3.1 Cache Memory
Feature
Options
Description
Cache System Bios area
Uncached, Write Protect
Controls caching of system bios area
Cache Video Bios area
Uncached, Write Protect
Controls caching of video bios area
Cache D000 – D3FF
Cache D400 – D7FF
Cache D800 – DBFF
Cache DC00 - DFFF
Disabled,
Write Through,
Write Protect,
Write Back
Disabled = This block is not cached.
Write through = Writes are cached
and sent to main memory at once.
Write Protect = Writes are ignored.
Write Back = Writes are cached but
not sent to main memory until
necessary.
5.2.3.2 CPU Control Sub-Menu
Note : Some options can be different dependent on used type of CPU
Feature
Hyperthreading
Options
Disabled, Enabled
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Description
Enabling Hyperthreading activates
additional CPU threads. These threads
may appear as additional processors
but will share some resources with
other threads within the physical
package.
ETE-PV510
Rev. 1.8
Feature
Processor Power
Management
Options
Disabled,
EIST only,
C-States Only,
Enabled
User Manual
Description
Selects the Processor Power
Management desired:
Disabled = C-States and EIST are
disabled. Boot with maximum CPU
speed.
EIST Only = C-States are disabled.
C-States Only = EIST is disabled.
Enabled = C-States und EIST are
enabled.
Note: EIST refers to the speed step
capability of the CPU. Only N450
supports EIST.
Enhanced C-States
Enable
Enabled, Disabled
Enables Enhanced C-State
No Execute Mode Mem
Protection
Enabled, Disabled
When enabled and OS supports the
feature, the OS can set memory pages
as not executable.
Set Max Ext CPUID = 3
Disabled, Enabled
Sets Max CPUID extended function
value to 3.
Enable Memory Gap
Disabled, Enabled
If enabled, a 1MB Memory Gap is
available at 15MB for use with an
option card.
5.2.3.3 Video (Intel IGD) Control Sub-Menu
Feature
Default Primary Video
Adapter
Options
Auto, IGD
Description
Select Auto to have Internal Graphics
if supported and enabled, be used for
the boot display device.
If PCI Video Card is connected, PCI
Video will be used. Select IGD to use
internal graphics if PCI Video Card is
connected.
IGD – Device 2
Disabled, Auto
IGD – Device 2, Function1 Disabled, Auto
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Enables or Disable the Internal
Graphics Device by setting item to the
desired value.
Enables or Disable Function 1 of the
Internal Graphics Device by setting
item to the desired value.
ETE-PV510
Rev. 1.8
Feature
IGD – Boot Type
IGD – LCD Panel Type
User Manual
Options
VBT default,
CRT,
LFP ,
CRT+LFP
640x480,
800x600,
1024x768
800x480,
1280x800,
1366x768,
Description
Select the Video Device that will be
activated during POST.
sp, 18bit
sp, 18bit
sp, 18bit
sp,18bit
sp,18bit
sp,18bit
Select the Local Flat Panel used by
the Internal Graphics Device by
selecting the appropriate setup item.
First Item is Panel 1, the last item is
panel 6.
IGD – Panel Scaling
Auto, Force Scaling, Off
Selects the LCD panel scaling option
used by the Internal Graphics Device.
1. Auto
2. Force Scaling
3. Off
IGD Backlight Brightness
0%, 10%, … 100%
Select the initial brightness for the
LVDS backlight signal.
DVMT 4.0 Mode
Fixed, DVMT, Auto
Select the configuration of DVMT 4.0
Graphics Memory that Driver will
allocate for use by the Internal
Graphics Device.
1. Fixed
2. DVMT
3. Auto
Pre-Allocated Memory
Size
8 MB
Select the amount of Pre-Allocated
Graphics Memory for use by the
Internal Graphics Device.
IGD Memory Size
128 MB, 256 MB
MaxDVMT ( only if DVMT
Mode is selected )
Select the amount of Total Graphics
Memory
DVMT Graphics Memory
N/A
Displays the Memory size of the Video
device.
Onboard EDID EEPROM
Disabled, Enabled
Enables or disables the Onboard EDID
EEPROM for LFP.
Pre-Allocated + Fixed + DVMT for use
by the Internal for use by the Internal
Graphics Device.
5.2.3.4 ICH Control Sub Menu
Feature
PnP Configuration
Options
Sub-Menu
Description
Configure PCI Control
PCI/PNP ISA UMB Region Sub-Menu
Exclusion
Reserve specific upper memory blocks
for use by legacy ISA devices
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Rev. 1.8
Feature
Options
User Manual
Description
PCI/PNP ISA IRQ
Resource Exclusion
Sub-Menu
Reserve specific IRQs for use by
legacy ISA devices
DMI Link ASPM Control
Disabled, Enabled
Enable/Disable the “Active State
Power Management” on DMI Link
between CPU and ICH8M.
If Enabled it may slightly reduce power
consumption, but may slightly delay
PCI or PCIe access cycles.
Pop Up Mode Enable
Disabled, Enabled
Select the proper mode:
If disabled, bus master traffic is a
break event and it will return from
C3/C4 to C0 based on break events.
If enabled, ICH will observe a bus
master request and it will take the
system from a C3/C4 state to a C2
state and auto enable bus masters.
Pop Down Mode Enable
Disabled, Enabled
Should be enabled only if Pop up is
enabled:
If disabled, ICH will NOT attempt to
automatically return.
If enabled, ICH will observe a NO bus
master request and it can return to a
previous C3 or C4 state.
Port 80h Cycles
LPC BUS, PCI BUS
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Control where Port 80h cycles are sent
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User Manual
5.2.3.5 PNP Configuration
Feature
PCI IRQ line 0:
Options
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Description
Select which interrupt should be
assigned to this PCI IRQ.
Devices: IGD, Secondary IDE, PCI
Slot 1
PCI IRQ line 1:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: Onboard Lan, PCI Slot 2
PCI IRQ line 2:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: PCI Slot 3
PCI IRQ line 3:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: PCI Slot 4
PCI IRQ line 4:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: ICH PATA Controller, UHCI
Controller 2
PCI IRQ line 5:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: ICH SATA Controller, UHCI
Controller 3, UHCI Controller 4
PCI IRQ line 6:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: HD Audio, SMBus
PCI IRQ line 7:
Auto Select, 3, 4, 5, 6, 7, 10,
11 ,12
Select which interrupt should be
assigned to this PCI IRQ.
Devices: UHCI Controller 1, EHCI
Controller 1
5.2.3.6 PCI/PNP ISA UMB Region Exclusion Sub-Menu
Feature
D000 – D3FF
D400 – D7FF
D800 – DBFF
DC00 – DFFF
Options
Available, Reserved
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Description
Reserve this block of upper memory
for use by legacy ISA devices.
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User Manual
5.2.3.6 PCI/PNP ISA IRQ Resource Exclusion Sub-Menu
Feature
Options
IRQ (3, 4, 5, 7, 9, 10, 11 Available, Reserved
12)
Description
Reserves the specified IRQ for use
by legacy ISA devices
Note : Chipset does not support ISA-DMA
5.2.3.7 ACPI Control Sub-Menu
Feature
Options
Description
Disable ACPI _Sx
None, S1, S2, S3, S5
Select one of the ACPI power states:
S1, S2,S3, S5. If selected, the
corresponding power state will be
disabled.
FACP – RTC S4 Flag
Value
Disabled, Enabled
Valid only for ACPI
FACP – PM Timer Flag
Value
Disabled, Enabled
Control the value for the RTC S4 flag
in the FACP Table
Valid only for ACPI
Controls the timer used by the OS
through the FACP Tables Flags.
This is now possible with WINXP
SP2 and beyond.
HPET Support
Disabled, Enabled
This field is valid only in the
WindowsXP OS.
Control the High Performance Event
Timer through this setup option
when enabled. The HPET Table will
then be pointed to by the RSDT and
the proper enable bits will be set.
HPET Base Address
0xFED00000,
0xFED01000,
0xFED02000,
0xFED03000
Select the Base Address for the High
Performance Event Timer.
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5.2.3.8 Integrated Device Control Sub-Menu
Feature
Options
Description
USB Ports
Disabled, Ports 0-1, Ports 0-3, Choose which Ports should be
Ports 0-5
enabled
USB 2.0
Disabled, Enabled
Enables USB 2.0 (EHCI) functionality
Azalia Audio
Disabled, Auto
Enables or disables onboard HD Audio
SATA Raid
Disbaled, Enabled
Enables SATA Raid Oprom.
To enter Raid Option Rom Setup press
CTRL-J after Post. After your Raid-Set
(0,1) is built exit the Raid Option Rom.
The Raid Volume will appear as PCI
SCSI device in the Boot Menu.
For XP installation a floppy is required
to load AHCI driver during setup by
pressing F6. Vista und Win7 have built
in drivers for installation.
It is recommended to install Intel
Matrix Storage Utility after installation
of Windows.
SATA AHCI Configuration
Disabled, Enabled
Enable AHCI Mode.
For XP Installation a Floppy is required
to load AHCI Driver during Setup by
pressing F6. Vista und Win7 have built
in drivers for Installation.
Disable Vacant Ports
Disabled, Enabled
Controls automatic disabling if vacant
SATA ports.
Primary IDE
Disabled, Enabled
Disables Primary IDE Interface
Secondary IDE OPROM
Disabled, Enabled
Enables or disables the OPROM of the
secondary IDE controller. When
disabled, attached drives are not
detected and not bootable.
On–board LAN
Disabled, Enabled
Controls Power to the onboard device.
Note: Re-enabling the LAN after it has
been disabled requires platform power
cycling.
PXE OPROM
Disabled, Enabled
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Enable PXE Option ROM.
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5.2.3.9 I/O Device Configuration Menu
Feature
Options
Description
Serial Port A
Disabled, Enabled,
Disabled = Disabled the device
Enabled = User configuration
Base I/O address
3F8, 2F8
Set the base I/O address for Serial
Port A.
Interrupt
3, 4
Set the interrupt for Serial Port A.
Serial Port B
Disabled, Enabled
Disabled = Disabled the device
Enabled = User configuration
Mode
Normal, IR, ASK-IR
Set the mode for Serial Port B (wired
/ infrared).
Base I/O address
3F8, 2F8
Set the base I/O address for Serial
Port B.
Interrupt
3, 4
Set the interrupt for Serial Port B.
Serial Port C
Disabled, Enabled, Auto
Disabled = Disabled the device
Enabled = User configuration
NOTE: Serial port C is available only if
a 2nd SuperIO chip is implemented on
the base board. Otherwise this menu
item is invisible.
Base I/O address
3E8, 2E8
Set the base I/O address for Serial
Port B.
Interrupt
10, 11
Set the interrupt for Serial Port B.
Serial Port D
Disabled, Enabled, Auto
Disabled = Disabled the device
Enabled = User configuration
NOTE: Serial port D is available only if
a 2nd SuperIO chip is implemented on
the base board. Otherwise this menu
item is invisible.
Base I/O address
3E8, 2E8
Set the base I/O address for Serial
Port B.
Interrupt
10, 11
Set the interrupt for Serial Port B.
Floppy Controller
or
Parallel Port
Disabled, Enabled
Disabled = Disabled the device
Enabled = User configuration
NOTE: The floppy controller shares
pins with the parallel port. Therefore,
depending on the status of the
LPT/FLPY# signal on pin 51 of the
ETX connector X3, either the floppy
controller entry or the parallel port entry
is visible.
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Feature
Options
User Manual
Description
Base I/O address
378, 278,
Set the base I/O address for Parallel
Port.
Interrupt
5, 7
Set the interrupt for Parallel Port.
Mode
Output only,
Bi-directional,
EPP, ECP
Set the mode for Parallel Port.
DMA channel
1, 3
Set the DMA channel for Parallel
Port (only available if mode was set
to ECP).
External Parallel Port
Disabled, Enabled
Disabled = Disabled the device
Enabled = User configuration
Base I/O address
378, 278,
Set the base I/O address for Parallel
Port.
3BC
Interrupt
5, 7
Set the interrupt for Parallel Port.
Mode
Output only,
Set the mode for Parallel Port.
Bi-directional,EPP
PS/2 Mouse
Disabled, Enabled
“Disabled” prevents any installed
PS/2 mouse from functioning, but
frees up IRQ 12.
“Enabled” forces the PS/2 mouse
port to be enabled regardless if a
mouse is present.
Warning: If the same I/O address or Interrupt is selected for more than one port, the
menu displays an asterisk (*) for the conflicting settings.
5.2.3.10
Clock Control Sub-Menu
Feature
Options
Description
CK-505 Clock Chip
Default, Program
Control Programming of the CK-505
Clock Chip.
Program = program values by Bios
Default= Use default values at
Power-On
Spread Spectrum mode
Off, On
Control programming of the Spread
Spectrum Mode bit in CK-505 chip.
0.5 Downspread if enabled.
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5.2.3.11
User Manual
Watchdog Options
Feature
Options
Description
Watchdog delay
1 second,
5 seconds,
10 seconds,
30 seconds
1 minute ,
5 minutes,
10 minutes,
30 minutes
After the watchdog is activated, it
waits the selected delay time before
it starts decrementing the timeout
period.
Watchdog timeout
0.4 second,
1 second,
5 seconds,
10 seconds,
30 seconds,
1 minute ,
5 minutes,
10 minutes
Select the maximum watchdog
trigger period.
If the watchdog is not triggered
before the end of this period, a
system reset will be generated.
Watchdog start on boot
No, Yes
Select if the watchdog should be
started at the end of POST.
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5.2.4 The Security Menu
Feature
Options
Supervisor Password Is Displays Supervisor
Password Is
Description
Displays the current status of the
Supervisor password (“Clear” or “Set”)
User Password Is
Displays User Password Is Displays the current status of the User
password (“Clear” or “Set”)
Set Supervisor
Password
Press return to enter
supervisor password
Supervisor Password controls access to
the setup utility.
Set User Password
Press return to enter user
password
User Password controls access to the
system at boot.
Password on boot
Disabled,
Enabled
Enables password entry on boot
TPM Support
Disabled,
Enabled
Enable Trusted Platform Module support.
Current TPM State
Displays Current TPM
State
Displays the current TPM status.
Change TPM State
No Change,
Enable & Activate,
Deactivate & Disable,
Clear
Changes TPM state.
Note: TPM options are only available if
TPM is assembled.
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5.2.5 The Power Menu
Feature
After Power Failure
Options
Stay Off,
Power On
Description
Sets the mode of operation if an AC power loss
occurs.
Power On will turn the power on as soon as the
power supply is back on.
Stay Off will keep the power off until the power
button is pressed.
Hardware Monitor
Sub-Menu
Configure Hardware Monitor
5.2.5.1 Hardware Monitor
Feature
Description
Voltage VIN4
Displays the current CPU voltage.
CPU Core Temperature
Sensor
Displays the current CPU temperature.
Memory Temperature
Sensor
Displays the current Memory Temperature.
Board Temperature Sensor
Displays the current board temperature.
FAN Speed
Displays the current fan speed.
Feature
Fan Control
Options
Disabled, Auto
Description
Fan Cruise Control
Auto: Fan speed is automatically controlled by
temperature
Disabled: Fan set to maximum speed
Fan Speed Zone 2
30%, 40%, 50% Fan speed control for temperature zone 2.
Fan Speed
Temperature Zone 2 = 40°C – 50°C
Fan Speed Zone 3
50%, 60%, 70% Fan speed control for temperature zone 3 (Medium
Fan Speed
temperature)
Temperature Zone 3 = 50°C – 60°C
Note: At Temperature Zone 4 (= >60°C) Fanspeed
is 100%
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5.2.6 The Boot Menu
After you turn on the computer, it will attempt to load the operating system (eg.
DOS, Windows XP, Linux, …) from a device listed in the boot priority order. If it cannot
find the operating system on that device, it will attempt to load from the next device in the
list.
Boot devices (i.e., with access to an operating system) can include: hard drives, floppy
drives, CD ROMs, removable devices (e.g. USB sticks), and network cards.
Note: Specifying a device as a boot device on the Boot Menu requires that an operating
system is loaded on that device.
Selecting "Boot" from the Menu Bar displays the Boot menu, which looks like this:
Feature
Boot priority order:
1: USB KEY:
2: USB CDROM:
3: USB HDD:
4: IDE HDD:
5: IDE CD:
6: PCI SCSI:
7: PCI BEV:
Exclude from boot order:
Description
Boot priority order for next boot. System tries to boot the
first bootable device in this list.
Use <+> and <-> to change order.
Use <x> to exclude or include a device from/to the boot
priority list.
Use <Shift + 1> to enable or disable a device.
Use <1 – 4> to load default boot sequence.
System does not try to boot a device from this list.
: USB LS120:
: PCI BEV:
: Legacy Network Card:
: Legacy
Pressing the “F10” key during the bios boot phase will bring up the bios boot menu, which
will allow you to select a different boot device for the current boot process only. In this
boot menu, only devices in the “Boot priority list” will be selectable. Devices excluded
from the boot order will not be shown.
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5.2.7 The Exit Menu
The following sections describe each of the options on this menu. Note that <Esc> does
not exit this menu. You must select one of the items from the menu or menu bar to exit.
Exit Saving Changes
After making the selections in the Setup menus, always select "Exit Saving Changes".
This procedure stores the options displayed in the menus in CMOS ( battery-backed
CMOS RAM) a special section of memory that stays alive after you turn the system off.
The next time you boot the computer, the BIOS configures the system according to the
Setup parameters stored in CMOS.
If you attempt to exit without saving, the program asks if you want to save before exiting.
During boot-up, the Phoenix BIOS attempts to load the values saved in CMOS. If those
values cause the system boot to fail, reboot and press <F2> to enter Setup. In Setup, you
can reload the Default Values (as described below) or try to change the selections that
caused the boot to fail.
Exit Discarding Changes
Use this option to exit Setup without storing in CMOS any new selections have been
made. The selections previously in effect remain valid.
Load Setup Defaults
To display the default values for all the Setup menus, select "Load Setup Defaults" from
the Main Menu.
If, during boot-up, the BIOS program detects a problem in the integrity of values stored in
CMOS, it displays this message:
System CMOS checksum bad - run SETUP Press <F1> to resume, <F2> to Setup
The CMOS values have been corrupted or modified incorrectly, perhaps by an
application program that changes data stored in CMOS.
Press <F1> to continue the boot process with the ROM default values already loaded or
<F2> to run Setup and change the current settings.
Discard Changes
If, during a Setup Session, you change your mind about changes you have made and
have not yet saved the values to CMOS, you can restore the values previously saved to
CMOS.
Selecting “Discard Changes” on the Exit menu restores all the selections to their previous
values.
Save Changes
Selecting “Save Changes” saves all the selections without exiting Setup. You can return
to the other menus if you want to review and change the selections.
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5.3
Rev. 1.8
User Manual
Bios Update
If a System-BIOS update is required please follow these instructions:
1.) Create a bootable DOS disk/usb-stick/hdd.
2.) Copy PHLASH16.EXE, BIOS.WPH and UPDATE.BAT to this device.
3.) Boot the system from this device.
4.) Type "update.bat" to update the System BIOS.
Note: If a window with UUID message pops up, press enter to skip this message.
Otherwise it takes up to one minute till this message window closes automatically. When
the UUID message window is closed, the bios update process continues.
5.) When the BIOS update has finished, reboot the system.
Note: After the system has been updated, the CMOS settings are changed back to
default values and therefore it is necessary to enter Setup (press F2 at boot time) to
reconfigure the system settings.
5.4
Bios Crisis Recovery
Should the BIOS setup be altered, such that it is no longer possible to re-enter the BIOS
setup – for example if the wrong display is selected, the following methods can be used to
restore the default settings:
1. Blind reset to defaults
2. Crisis recovery / clear backup EEPROM jumper
3. Crisis recovery software (usually only necessary if the BIOS is corrupted – for
example if power was removed during a BIOS update)
5.4.1 Blind Reset to defaults
In the event that there is no display or the display is for some reason not active, in order
to get the BIOS back to the default settings (and so enable the display) the following
sequence must be performed:
1. During boot, press F2 to get into BIOS setup (F2 can be pressed repeatedly, if
a beeper is installed, press F2 until setup entry will be signalled with a beep)
2. Press F9 and then enter to reset to default settings
3. Press F10 and then enter to save and exit the BIOS setup
4. System should then reboot with the default settings.
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5.4.2 Crisis Recovery / Clear backup EEPROM Jumper
See photo below to find the Crisis Recovery or Clear backup EEPROM Jumper.
The two pads of this jumper should be shorted (using tweezers or pliers) before applying
power to the board and held shorted until the crisis recovery has started. As soon as crisis
recovery is started (indicated by a long beep ) the short can be removed and the system can
be restarted.
It is also possible to use a recovery dongle ( USB dongle or RS232 dongle), instead of
shorting the jumper to reset the EEPROM. An USB dongle can be obtained from MSC.
To create a RS232 following pins must be routed : 2-3; 6-7; 4-8-9.
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5.4.3 Crisis Recovery software
This technique should only be required in the event of a serious corruption of the BIOS – for
example following an unsuccessful attempt to update the BIOS
To use this technique a special software – CRISDISK and a USB dongle or RS232 Dongle
must be obtained from MSC.
Note: Contact the MSC customer support for information how to obtain the CRISDISK.ZIP
software and the USB recovery dongle or RS232 recovery dongle.
Please follow these simple steps to create a bootable crisis recovery medium:
1. Unzip CRISDISK.ZIP and start the windows-based program WINCRIS.EXE on the
host system. A window will pop up as shown below:
2. In the drop-down box, select “Removable Disk 0 (xxxMb)” to create a recovery USB
stick. Disk options should be left as “Create MINIDOS Crisis Disk”.
3. Press the start button to generate the selected crisis recovery medium.
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Proceed as follows to use the generated USB stick for the recovery :
Plug the USB/RS232 dongle into a free USB port on the failing system before switching
the system on. Please make sure that you use different USB controllers for USB dongle
and USB crisis recovery medium. After power-up, crisis recovery mode should start
automatically.
The programming process is signalled by short beeps and terminated after successfull
programming with one long beep. To avoid a recovery loop it is recommended to remove the
USB Controller after the first long beep after programming has been started.
After the second long beep, the system is automatically rebooted.
Important Notes:
USB recovery dongle and USB crisis recovery device must not be plugged into the
same USB controller.
Crisis recovery may take up to 5 minutes
A long beep indicates a successful recovery.
Crisis recovery does not include the bootblock.
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5.5
Rev. 1.8
User Manual
Diagnostics Postcodes
Postcodes can be seen on a special Postcode display, either on the MSC mainboard or on
an external Postcode PCI card. There is an item in the bios setup to select the bus that
should receive the postcode data: either PCI (for external cards) or LPC (for onboard
displays).
If a postcode display has only 2 digits, only the lower byte of word-value postcodes will be
shown.
5.5.1 Bootblock Bios Postcodes
Code
BBH
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
95h
96h
97h
99h
Bootblock Task Description
Bootblock Early Init after Reset
Chipset Init
Bridge Init
CPU Init
System Timer Init
System I/O Init
Check forced Recovery Boot, CMOS & CMOS Backup Clear
Check BIOS Checksum
Goto BIOS, start early BIOS initialzations
Init Multi Processor
Set Huge Segment
OEM Initializations
Init Interrupt and DMA Controller
Init Memory Type
Init Memory Size
Shadow Boot Block
Init SMM
System Memory Test
Init Interrupt Vectors
Init Realtime Clock
Init Standard Video
Init Beeper
Initialize USB Controller
Init Boot
Clear Huge Segment
Boot OS
Init Security
5.5.2 System Bios Postcodes
Code
04h
03h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Eh
Beeps
POST Task Description
Get CPU type
Disable Non-Maskable Interrupt (NMI)
Initialize system hardware
Disable shadow and execute code from the ROM.
Initialize chipset with initial POST values
Set IN POST flag
Initialize CPU registers
Enable CPU cache
Initialize caches to initial POST values
Initialize I/O component
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Code
0Fh
10h
11h
12h
13h
14h
16h
17h
18h
1Ah
1Ch
20h
22h
24h
28h
29h
2Ah
2Ch
2Eh
2Fh
32h
33h
36h
38h
3Ah
3Ch
3Dh
41h
42h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Eh
4Fh
50h
51h
52h
54h
55h
58h
59h
5Ah
5Bh
5Ch
60h
62h
64h
66h
67h
68h
Rev. 1.8
Beeps
1-2-2-3
1-3-1-1
1-3-1-3
1-3-4-1
1-3-4-3
2-1-2-3
2-2-3-1
POST Task Description
Initialize fixed disk drives
Initialize Power Management
Load alternate registers with initial POST values
Restore CPU control word during warm boot
Initialize PCI Bus Mastering devices
Initialize keyboard controller
BIOS ROM checksum
Initialize cache before memory Autosize
8254 timer initialization
8237 DMA controller initialization
Reset Programmable Interrupt Controller
Test DRAM refresh
Test 8742 Keyboard Controller
Set ES segment register to 4 GB
Autosize DRAM
Initialize POST Memory Manager
Clear 512 kB Base RAM
RAM Address test
Base RAM Test
Enable cache before system BIOS shadow
Compute CPU clock speed in MHz
Initialize Phoenix Dispatch Manager
Warm start shut down
Shadow system BIOS ROM
Autosize cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialize RomPilot
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Initialize I20 support
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Initialize MultiBoot
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Configure USB devices
Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
Conventional memory test
Extended memory test
Address Test on Extended Memory
Jump to UserPatch1
Configure advanced cache registers
CPU feature, MP, and APIC initialization
Enable external and CPU caches
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Code
69h
6Ah
6Bh
6Ch
70h
72h
76h
7Ch
7Dh
7Eh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Fh
90h
91h
92h
93h
95h
96h
97h
98h
99h
9Ah
9Ch
9Dh
9Eh
9Fh
A0h
A2h
A4h
A8h
AAh
ACh
AEh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
Rev. 1.8
Beeps
1-2
User Manual
POST Task Description
Setup System Management Mode (SMM) area
Display external L2 cache size
Load custom defaults (optional)
Display BIOS shadow status
Display error messages
Check for configuration errors
Check for keyboard errors
Set up hardware interrupt vectors
Initialilze Intelligent System Monitoring
Initialize coprocessor if present
Disable onboard Super I/O ports and IRQs
Late POST device initialisation
Detect and install external RS232 ports
Configure non-MCD IDE controllers
Detect and install external parallel ports
Initialize PC-compatible PnP ISA devices
Re-initialize onboard I/O ports.
Configure Motheboard Configurable Devices (optional)
Initialize BIOS Data Area
Enable Non-Maskable Interrupts (NMIs)
Initialize Extended BIOS Data Area
Test and initialize PS/2 mouse
Initialize floppy controller
Determine number of ATA drives (optional)
Initialize hard-disk controllers
Program timing registers according to PIO modes
Jump to UserPatch2
Build MPTABLE for multi-processor boards
Install CD ROM for boot
Clear huge ES segment register
Fixup Multi Processor table
Enable PCI devices and ROM Scan One long, two short
beeps on checksum failure
Check for SMART Drive
Shadow option ROMs
Set up Power Management
Initialize security engine (optional)
Enable hardware interrupts
Determine number of ATA and SCSI drives
initialize IGD Graphics Device, initialize MRC Parameter
Frame
Check key lock
Initialize typematic rate
Erase F2 prompt
Scan for F2 key stroke
Enter SETUP
Clear Boot flag
Check for errors
Inform RomPilot about the end of POST.
POST done - prepare to boot operating system
store enhanced CMOS values in non-volatile area
1 One short beep before boot
Terminate QuietBoot (optional)
Check password (optional)
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Code
B7h
B9h
BAh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
D2h
E0h
E1h
Rev. 1.8
Beeps
POST Task Description
Initialize ACPI BIOS
Prepare Boot
Initialize DMI parameters
Clear parity checkers
Display MultiBoot menu
Clear screen (optional)
Check virus and backup reminders
Try to boot with INT 19
Initialize POST PEM Error Manager
Initialize PEM error logging
Initialize error PEM display function
Initialize PEM system error handler
PnPnd dual CMOS (optional)
Initialize note dock (optional)
Initialize note dock late
Force check (optional)
Extended checksum (optional)
Redirect Int 15h to enable remote keyboard
Redirect Int 13h to Memory Technologies
Redirect Int 10h to enable remote serial video
Remap I/O and memory for PCMCIA
Initialize digitizer and display message
Unknown interrupt or exception
DIMM Type Detection Error
Memory Configuration Error
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User Manual
5.5.3 Memory Detection Postcodes
Code
Calistoga Memory Detection
FFA0h
Start memory detection
FF01h
Enable MCHBAR
FF02h
Check for DRAM initialisation interrupt and reset fail
FF03h
Verify all DIMMs are DDR2 and unbuffered
FF04h
Detect an improper warm reset and handle
FF05h
Detect if ECC SO-DIMMs are present in the system
FF06h Verify all DIMMs are single or double sided and not asymmetric
FF07h
Verify all DIMMs are x8 or x16 width
FF08h Find a common CAS latency between the DIMMS and the MCH
FF09h Determine the memory frequency and CAS latency to program
FF10h
Determine the smallest common TRAS for all DIMMs
FF11h
Determine the smallest common TRP for all DIMMs
FF12h
Determine the smallest common TRCD for all DIMMs
FF13h
Determine the smallest refresh period for all DIMMs
FF14h
Verify burst length of 8 is supported by all DIMMs
FF15h
Determine the smallest tWR supported by all DIMMs
FF16h
Determine DIMM size parameters
FF17h
Program Graphics frequency and PLL settings
FF18h
Program system memory frequency
FF19h
Determine and set the mode of operation for the memory
channels
FF20h
Program clock crossing registers
FF21h
Disable Fast Dispatch
FF22h Program the DRAM Row Attributes and DRAM Row Boundary
registers
FF23h
Program the DRAM Bank Architecture register
FF24h
Program the DRAM Timing & and DRAM Control registers
FF25h
Program ODT
FF26h
Perform steps required before memory init
FF27h
Program the receive enable reference timing control register
Program the DLL Timing Control Registers , RCOMP settings
FF28h
Enable DRAM Channel I/O Buffers
FF29h
Enable all clocks on populated rows
FF30h
Perform JEDEC memory initialization for all memory rows
FF31h
Program PM Settings
FF32h
Perform additional steps required after memory init
FF33h
Program DRAM throttling and throttling event registers
FF34h
Setup DRAM control register for normal operation and enable
FF35h
Setup DRAM control register for normal operation and enable
FF36h
Enable RCOMP
FF37h
Clear DRAM initialization bit in the ICH
5.5.4 ACPI Postcodes
Code
03h
04h
05h
ABh
CDh
ACPI Codes
Enter Suspend State S3
Enter Hibernate State S4
Enter Softoff State S5
Enter Wakeup from Powerstate
End Wakeup from Powerstate
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