1. No category


XII2004
M-RAM
(Magnetoresistive – Random
Access Memory)
Information flux.
Information
Information
Information
transmission
Processing
storage
DRAM, MRAM
Magnetic (HDD)
Outside
word
Input
Information
Output
M-RAM
M. Bernacki, S. Wąsek
Optical (CD, DVD)
Memory categories.
WHY DO WEE NEED
M-RAM MEMORY ????
M-RAM
M. Bernacki, S. Wąsek
Basic attractions
of M-RAM.




Nonvolatility;
Speed;
Low-power consumption;
Scalability.
M-RAM
M. Bernacki, S. Wąsek
Basic attractions
of M-RAM.
Transfer data to microprocessor
without
creating a bottleneck!
M-RAM
M. Bernacki, S. Wąsek
History and development...
M-RAM based on:
 M-RAM – quick view.
 
AMR
effect - 80-th.
Magnetoresistivity.
 GMR effect - 80-th.
 TMR effect – 1995 year.
M-RAM
M. Bernacki, S. Wąsek
Storage and states of a bit.
MRAM: charge and spin.
Storage state:
[%]
Soft ferromagnet


TMR

Insulator
DRAM: charge of capacitor.
„1”
Flash, EEPROM: charge on floating gate. Hard ferromagnet
FeRAM: charge of a ferroelectric capacitor.
„0”
Field
[Oe]
M-RAM
M. Bernacki, S. Wąsek
Implementation
of 1-MTJ / 1-transistor cell.
NiFe (free layer)
Al2O3 (tunneling barrier)
SAF
CoFe (fixed layer)
Ru
CoFe (pinned layer)
Word
line
I I
HHclad

unclad   2 H clad
w2  w
M-RAM
M. Bernacki, S. Wąsek
Write.
Word
line
Without digit line
current
M-RAM
M. Bernacki, S. Wąsek
With digit line
current
Word
line
RA [kOhm-um2]
Write.
Easy axis field [Oe]
M-RAM
M. Bernacki, S. Wąsek
Read.
Word line
Word
line
M-RAM
M. Bernacki, S. Wąsek
Sizes of MTJ.
4nm
NiFe (free layer)
1..2nm
Al2O3 (tunneling barrier)
3nm
Ferromagnet I
Tunnel barrier
CoFe (fixed layer)
Ru
3nm
CoFe (pinned layer)
M-RAM
Ferromagnet II
M. Bernacki, S. Wąsek
Other MRAM cell
architectures.
Twin cell arrays:
 Circuit is faster than the 1T1TMR implementation.
 Less atractive on a cell density and cost basis.
Diode cell:
 SOI diodes allow the integration of a memory with most
circuits without sacrificing silicon wafer surface area.
 SOI diodes suitable for this aplication haven’t been developed yet.
Transistorless array:
 Large reduce in cell area.
 Complex circuity required to read bit state, slow read.
M-RAM
M. Bernacki, S. Wąsek
MRAM 32Kb
memory segment.
Bit
line 0
Bit line
31
Digit
line
Word line
Word line
Digit
line
M-RAM
M. Bernacki, S. Wąsek
Reference generator.
Bit
line
RMAX
RMIN
Digit
line
Word
line
Word
line
Digit
line
RMAX
M-RAM
RMIN
M. Bernacki, S. Wąsek
RREF = 1/2(RMAX + RMIN)
1Mb MRAM architecture.
Available modes:
Active mode
Sleep mode
Standby mode
M-RAM
M. Bernacki, S. Wąsek
Examples and performance
of M-RAM technology.
 Motorola semiconductors –2002.
5-level metal CMOS,
copper interconnects;
 Technology:
Freescale 0.6um,
semiconductors
–2003/2004.
Technology:
Capacity:
1MB0.18mikrons, 5-level metal CMOS, copper interconnects;
Capacity:
4MB;
Access
time:
35ns
Access time: 15-20ns
M-RAM
M. Bernacki, S. Wąsek
Roadmap to future
storage technologies.
RRAM
with
CMR
M-RAM
M. Bernacki, S. Wąsek
Bio – MRAM,
vision for tomorrow?
Biomolecule labeled by magnetic markers
MRAM array
M-RAM
M. Bernacki, S. Wąsek
References.

Wykład z przedmiotu „Magnetyczne nośniki pamięci”, AGH;

Materiały z Uniwersytetu Bielefeld: wykład „Thin films and nanostructures”;

Materiały seminaryjne z „Motorola Labs”;

Materiały z sympozjum „VLSI symposium 2002”;

www.freescale.com

www.motorola.com
M-RAM
M. Bernacki, S. Wąsek
Dziękujemy za uwagę 
M-RAM
M. Bernacki, S. Wąsek