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8086
6 ARCH
HITEC
CTUR
RE
M
M.S.NAN
NDA
R
RESEARCH
H ASSITAN
NT
INDEX
X
Introducttion to 8086
8
1.
II.
8085
5 vs 8086
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IIIIT- HYDER
RABAD
8
8086
Arcchitecturre Functiional dia
agram
1.
2
2.
Execu
ution Unitt
Bus Interface
I
U
Unit
III. Pin
P descrription off 8086
Chapter1
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Pin diagram
d
off 8086
Comm
mon functtion signals
Minimum and Maximum
m mode sig
gnals
In
ntroducttion to 8086
8
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1.
2
2.
3
3.
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The
8086 is
i a 16-bitt micropro
ocessor, devveloped byy Intel Com
mpany. Th
he
first Inteel 4-bit 4004 microp
processor w
was introdu
uced in 197
71. The miccroprocesso
or
released
d after 40
004 was 8-bit micrroprocessorr 8008 in
n 1972. 8085
8
8 bit
b
microprrocessor is next
n
genera
ation of 8008 and theen 8085 is ffollowed byy 8086 16b
bit
processo
or which is more advan
nced than the
t previous versions.
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8085 vs 8086:
The main differences between 8085 and 8086 are given below:
8086 processor
8 bit processor
16bit processor
2.
3.
16 bit address lines
The clock speed of is 3MHz
4.
5.
6.
7.
Has 5 flags
Duty cycle:50%
6500 transistors
Accumulator based architecture
8.
Has one mode of operation
20-bit address lines
vary between 5, 8 and 10 MHz for three
different microprocessor
Has 9 flags
Duty cycle:33%
29000 transistors
general purpose registers based
architecture
Has two modes of operation: Maximum
and minimum
Can add more than one processor to the
existing processor.
Cant interface one more processor
Chapter 2
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8085 processor
1.
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8086 Architecture Functional diagram
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8086 microprocessor has two units; Execution Unit (EU) and Bus Interface Unit
(BIU). They are dependent and get worked by each other.
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Execution Unit (EU)
Execution unit receives program instruction codes and data from the Bus
Interface Unit (BIU), executes them and stores the results in the general registers. It
can also store the data in a memory location or send them to an I/O device by
passing the data back to the BIU. This unit, EU has no connection with the system
Buses. It receives and outputs all its data through BIU.
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ALU (Arithmetic and Logic Unit)
This unit performs various arithmetic and logical operations, based on the
instruction to be executed. The ALU can perform arithmetical operations, such as
add (+), subtract (-), increment, decrement, convert byte/word and compare etc and
logical operations, such as AND, OR, exclusive OR, shift/rotate and test etc.
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Registers
A register is like a memory location to store the data or instructions. These
registers are denoted by the name rather than numbers. It has 4 data registers (AX,
BX, CX, DX), two pointer registers (Stack Pointer (SP), Base Pointer (BP)), two index
registers (Source Index (SI), Destination Index (DI)), one temporary register and one
status register FLAGS.
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AX (Accumulator), BX (Base), CX (Count) and DX (Data) registers has 2
separate 8-bit registers to access the high and low bytes of data. The high byte of AX
is called AH and the low byte is AL. Similarly, the high and low bytes of BX, CX, and
DX are BH & BL, CH & CL, and DH & DL respectively.
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All the Data, Pointer, Index and Status registers are 16 bit registers. The
Temporary register holds the operands for the ALU and the individual bits of the
FLAG registers reflect the result of a computation.
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Bus Interface Unit (BIU)
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As the Execution Unit (EU) has no connection with the system Busses, this job
is done by BIU. BIU and EU are connected with an internal bus. BIU connects EU
with the memory or I/O circuits. It is responsible for transmitting data, addresses
and control signal on the busses.
Registers
BIU has 4 segment registers: Code Segment (CS), Data Segment (DS), Stack
Segment (SS), and Extra Segment (ES). All these 4 segment registers holds the
addresses of instructions and data in memory. These values are used by the
processor to access memory locations. It also contains one pointer register: the
Instruction Pointer (IP). IP contains the address of the next instruction to be
executed by the EU.
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Instru
uction Qu
ueue
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When
the EU
E executess instructio
ons, the BIIU gets up to 6 bytess of the nex
xt
instructiion and sttores them in the instruction queue
q
and this proceess is calleed
instruc
ction pre-ffetch. Thiss is processs speeds up
p the processsor perforrmance. Alsso
when th
he EU need
ds to be co
onnected w
with memo
ory or perip
pherals, BIIU suspend
ds
instructiion pre-fetcch and perfforms the needed operrations.
Piin Desc
cription
n of 808
86
Chaptter 3
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Pin diagram of
o 8086:
ure: Pin Diagram
D
o 8086
of
Figu
The 808
86 operatees in singlee processorr or multip
processor cconfiguration mode tto
achieve high perforrmance. Th
hese pins seerve a partiicular functtion in Min
nimum Mod
de
(single processor mode and
d other fu
unction in Maximum
m Mode configuratio
on
(multiprrocessor mode).
m
Thee following
g pin fun
nction desccriptions are
a
for th
he
microprrocessor 8086 in eitherr minimum
m or maximu
um mode.
Signa
al Grou
ups
The 808
86 signals can be categ
gorized in th
hree groupss.
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1. Signals havee Common functions
f
in
n Minimum
m as well as Maximum
m Mode.
2. Signals having special functions
f
fo
or Minimum
m Mode
f
fo
or Maximum
m Mode.
3. Signals having special functions
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Figu
ure: Signa
al groups of
o 8086
Common fu
unction
n signa
als
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AD15 – AD0 (I/O
O): Addres
ss Data Bu
us
T
These
lines are the tim
me multipleexed memo
ory/IO Add
dresses durring the firsst
clock cyycle T1 and DATA durring T2, T3
3 and T4 cllock cycles.. These linees are activve
and flo
oat to tri-state durring interrrupt ackno
owledge aand local bus "Holld
acknowlledge".
A19/S6
6, A18/S5, A17/S4, A16/S3
A
(0)): Address
s/Status
D
During
T1 state
s
these lines are the four most
m
signifiicant addreess lines fo
or
memoryy operations. During I/O
I
operatio
ons these liines are low
w. During memory
m
an
nd
I/O operrations, sta
atus informa
ation is ava
ailable on th
hese lines in
n T2, T3, an
nd T4 statess.
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S6:
When S6 is Low, it indicates that 8086 is in control of the bus. During a "Hold
acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another
bus master to take control of the status bus.
S5:
S4 & S3:
Lines are decoded as follows:
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The status of the flag is indicated through this bus. The status of the interrupt
enable flag bit is updated at the beginning of each cycle.
A16/S3
Function
0
0
Extra segment access
0
1
1
0
1
1
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A17/S4
Stack segment access
Code segment access
Data segment access
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After the first clock cycle of an instruction execution, the A17/S4 and A16/S3
pins specifies which segment register generates the segment portion of the 8086
address. By decoding these lines and using the decoder outputs, the chip selects for
memory chips up to 4 Megabytes (one Megabyte per segment) of memory to be
accessed.
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This feature also provides a degree of protection by preventing write
operations to one segment from erroneously overlapping into another segment and
destroying information in that segment.
BHE /S7 (0): Bus High Enable/Status
0: BHE
1: S7
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•
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During the T1 state, the BHE should be used to enable data onto the most
significant half of the data bus (D15 - D8). 8-bit oriented devices tied to the upper
half of the bus would normally use BHE to control chip select functions. BHE is Low
during T1 state of read, write and interrupt acknowledge cycles when a byte is to be
transferred on the high portion of the bus.
The S7 status information is available during T2, T3 and T4 states. The signal
is active Low and floats to 3-state during "hold" state. This pin is Low during T1 state
for the first interrupt acknowledge cycle.
RD (0): READ
The Read strobe indicates that the processor is performing a memory or I/O
read cycle. This signal is active low during T2 and T3 and Tw states of any read cycle.
This signal floats to tri-state in "hold acknowledge cycle".
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TEST (1):
• TEST pin is Low: Execution continues.
• TEST pin is High: Processor waits in an "idle" state.
TEST pin is examined by the "WAIT" instruction. This input is synchronized
internally during each clock cycle on the leading edge of CLK.
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INTR (1): Interrupt Request
This signal is active HIGH. It is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the processor should
enter into an interrupt acknowledges operation. A subroutine is vectored to an
interrupt vector look up table located in system memory. It can be internally masked
by software, by resetting the interrupt enable bit INTR which is internally
synchronized.
NMI (1): Non-Maskable Interrupt
An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to
via the interrupt vector look up table located in system memory. NMI is not
maskable internally by software. A transition from a LOW to HIGH on this pin
initiates the interrupt at the end of the current instruction. This input is internally
synchronized.
Reset (1)
Reset causes the processor to immediately terminate its present activity. Then it :
•
•
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Initializes registers DS, SS, ES, IP and flags to all zeros.
Initializes CS to FFFF H.
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Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next
instruction from the 20 bit physical address FFFF0H.
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Ready (1)
This is active HIGH signal. Ready is the acknowledgement from the addressed
memory or I/O device that it will complete the data transfer.
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CLK (1): Clock
The Clock provides the basic timing for the processor and bus controller. The
minimum frequency of 2 MHz is required. The maximum clock frequencies of the
8086-4, 8086 and 8086-2 are 4MHz, 5MHz and 8MHz respectively.
MN/MX (1): Maximum / Minimum
This pin indicates that operation mode of the processor. In minimum mode,
the 8086 itself generates all bus control signals. In maximum mode the three status
signals are to be decoded to generate all the bus control signals.
•
•
MN/ MX = 1: Minimum Mode
MN/ MX = 0: Maximum Mode
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Minimum mode signals
M/IO (0): Status line
This pin describes the access of a memory or an I/O.
•
•
M/IO = 0: I/O access
M/IO = 1: Memory access
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M / IO become valid in the T4 state preceding a bus cycle and remain valid
until the final T4 of the cycle.
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WR (0): Write
It is active LOW. This indicates that the processors is performing either a
write memory or write I/O cycle, depending on the state of the M /IO signal. WR is
active for T2, T3 and Tw of any write cycle.
INTA (0): Interrupt Acknowledge
• It is used as a read strobe for interrupt acknowledge cycles.
• It is active LOW during T2, T3, and T4 of each interrupt acknowledge cycle.
ALE (0): Address Latch Enable
• ALE is provided by the processor to latch the address into the 8282/8283
address latch.
• ALE will be in active high pulse during T1 of any bus cycle.
• ALE signal is never floated.
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DT/ R (0): DATA Transmit/Receive
• DT/R is used to control the direction of data flow through the transceiver.
• This signal floats to tri-state off during local bus "hold acknowledge".
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DEN (0): Data Enable
• DEN is active LOW during each memory and IO access.
• It will be low beginning with T2 until the middle of T4, while for a write cycle
and active from the beginning of T2 until the middle of T4.
• It floats to tri-state off during local bus "hold acknowledge".
HOLD & HLDA (I/O): Hold and Hold Acknowledge
Hold indicates that another master is requesting a local bus "HOLD". To be
acknowledged, HOLD must be active HIGH. The processor receiving the "HOLD”
request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1clock cycle. Simultaneous with the issue of HLDA, the processor will float the local
bus and control lines. After "HOLD" is detected as being Low, the processor will
lower the HLDA and when the processor needs to run another cycle, it will again
drive the local bus and control lines.
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Maximum mode signals
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S2, S1, S0 (0): Status Pins
• These pins are active during T4, T1 and T2 states and is returned to passive
state (1,1,1) during T3 or Tw (when ready is inactive).
• These are used by the 8288 bus controller to generate all memory and I/O
operation access control signals.
• Any change by S2, S1, and S0 during T4 is used to indicate the beginning of a
bus cycle.
S1
S0
Characteristics
0
0
0
Interrupt acknowledge
0
0
1
Read I/O port
0
1
0
Write I/O port
0
1
1
Halt
1
0
0
Code access
1
0
1
Read memory
1
1
0
Write memory
1
1
1
Passive State
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S2
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QS0, QS1 (0): Queue – Status
Queue Status is valid during the clock cycle after which the queue operation is
performed. QS0, QS1 provide status to allow external tracking of the internal 8086
instruction queue. Since instructions are executed from the 8086 internal queue, the
queue status is presented each CPU clock cycle and is not related to the bus cycle
activity. This mechanism allows
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1. A processor to detect execution of an ESCAPE instruction which directs
the co- processor to perform a specific task
2. An in-circuit Emulator to trap execution of a specific memory location.
QS1
QS2
Characteristics
0
0
No operation
0
1
First byte of opcode from queue
1
0
Empty the queue
1
1
Subsequent byte from queue
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LOCK (0)
• LOCK is active Low signal. It indicates to another system bus master, not to
gain control of the system bus.
• The LOCK signal is activated by the "LOCK" prefix instruction and remains
active until the completion of the instruction.
• This signal floats to tri-state OFF during 'hold acknowledge'.
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RQ/GT0 and RQ/GT1 (I/O): Request/Grant
• These pins are used by other processors in a multi-processor organization.
• Local bus masters of other processors force the processor to release the local
bus at the end of the processors current bus cycle.
• Each pin is bi-directional and has an internal pull up resistors. Hence they
may be left un-connected.
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