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Avoiding Assign Statements in Verilog Netlists
The assign statement in Verilog allows two nets or ports to be connected to each other. In a netlist this
occurs in one of two cases:
An input port entering a module is directly connected to an output port without any logic in between:
assign MonitorxSO = ControlInxSI
A signal within a module is connected to one or more output ports directly.
assign ScanOutxTO = DataxD
assign DataOutxDO = DataxD
Why are assign statements undesired in netlists ?
During simple back-end flows the netlist is flattened (the hierarchy is removed) for the processing. The tool
keeps the hierarchy information during processing and once the back-end design flow is complete, the
resulting final netlist will still contain the original hierarchy.
Both cases described above are essentially a result of a mistake in how the module inputs anf outputs were
defined. In the first case, you would not need an input if the signal is not used within this module, and in the
second case the additional output(s) were unnecessary.
Once the netlist is flattened these connections practically disappear. The tool may perform optimizations
which will change parts of the netlist (inserting buffers, changing drive strengths, re-synthesizing parts of
the path) while still keeping the original hierarchy intact. Re-creating the hierarchy at this level is not easy.
What does the setDoAssign do ?
In a cockpit hierarchy the file
encounter/enc.tcl
contains the defaults that will be used by encounter during startup. In this file, the command setDoAssign
determines what will be done with assign statements in the netlist.
setDoAssign on -buffer BUFX1_or_similar
will instantiate a physical buffer (named BUFX1) to replace the assign statements. This removes all the
assign statements, and the hierarchical netlist can easily be processed. Sometimes problems occur,
especially when the input/output of such an assign buffer is optimized away, the assign buffer will still be
kept.
setDoAssign off
will try to preserve the assign statements. In some cases the resulting netlist will have problems.
In short neither of the solutions is foolproof. It would be better to minimize the number of assign statements
as much as possible.
How can Assign statements be removed ?
The easiest approach is to be carefull with the VHDL source code. Do not allow feedthroughs in your
design hierarchy. Analyze your results, sometimes parts of your code will be optimized away, resulting in
feedthroughs, or multiple connected outputs. Once you realize these are not needed, you can remove them
from your source as well.
The assign statements will be removed if you remove the offending hierarchy. There are very good reasons
to use a hierarchy, so please do not remove all the hierarchy in the design just to combat a few assign
statements.
You can use the command:
set_fix_multiple_port_nets -all -buffer_constants
in Synopsys Design Compiler prior to compile commands. This will in fact instantiate buffers for places
where assign statements would be used. Obviously this will add few extra gates to your design.
How do I know if there are assign statements in
the netlist ?
While you are writing out the verilog netlist, you will receive a warning:Warning:
Verilog 'assign' or 'tran' statements are written out. (VO-4)
Once you have the netlist you can use the grep command to look for assign within the netlist. If the
command returns you results you have assign statements.
grep -i assign netlist.v